From: Daniel Kirschten Date: Sun, 12 Apr 2020 20:51:29 +0000 (+0200) Subject: Merged LD and _RLD inputs of ModelAm2910RegCntr into one pin X-Git-Url: https://mograsim.net/gitweb/?p=Mograsim.git;a=commitdiff_plain;h=4eca3e207d12fcfab3a406d59aab940b37d6f324 Merged LD and _RLD inputs of ModelAm2910RegCntr into one pin --- diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910.json index 425805f9..4615e769 100644 --- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910.json +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910.json @@ -174,6 +174,15 @@ }, "params": 1 }, + { + "id": "NandGate", + "name": "NandGate#3", + "pos": { + "x": 90.0, + "y": 20.0 + }, + "params": 1 + }, { "id": "TriStateBuffer", "name": "TriStateBuffer#0", @@ -489,27 +498,6 @@ } ] }, - { - "pin1": { - "compName": "Am2910InstrPLA#0", - "pinName": "RLD" - }, - "pin2": { - "compName": "Am2910RegCntr#0", - "pinName": "LD" - }, - "name": "unnamedWire#11", - "path": [ - { - "x": 115.0, - "y": 105.0 - }, - { - "x": 115.0, - "y": 30.0 - } - ] - }, { "pin1": { "compName": "Am2910InstrPLA#0", @@ -519,7 +507,7 @@ "compName": "Am2910RegCntr#0", "pinName": "DEC" }, - "name": "unnamedWire#12", + "name": "unnamedWire#11", "path": [ { "x": 120.0, @@ -540,7 +528,7 @@ "compName": "WireCrossPoint#1", "pinName": "" }, - "name": "unnamedWire#13", + "name": "unnamedWire#12", "path": [ { "x": 230.0, @@ -557,7 +545,7 @@ "compName": "Am2910SP#0", "pinName": "STKI1" }, - "name": "unnamedWire#14", + "name": "unnamedWire#13", "path": [ { "x": 235.0, @@ -578,7 +566,7 @@ "compName": "Am2910SP#0", "pinName": "STKI0" }, - "name": "unnamedWire#15", + "name": "unnamedWire#14", "path": [ { "x": 230.0, @@ -595,7 +583,7 @@ "compName": "WireCrossPoint#1", "pinName": "" }, - "name": "unnamedWire#16", + "name": "unnamedWire#15", "path": [] }, { @@ -607,7 +595,7 @@ "compName": "WireCrossPoint#2", "pinName": "" }, - "name": "unnamedWire#17", + "name": "unnamedWire#16", "path": [ { "x": 200.0, @@ -624,7 +612,7 @@ "compName": "inc12#0", "pinName": "A" }, - "name": "unnamedWire#18", + "name": "unnamedWire#17", "path": [] }, { @@ -636,7 +624,7 @@ "compName": "sel4_12#0", "pinName": "I3" }, - "name": "unnamedWire#19", + "name": "unnamedWire#18", "path": [ { "x": 160.0, @@ -653,7 +641,7 @@ "compName": "sel4_12#0", "pinName": "I4" }, - "name": "unnamedWire#20", + "name": "unnamedWire#19", "path": [ { "x": 170.0, @@ -670,7 +658,7 @@ "compName": "sel4_12#0", "pinName": "I2" }, - "name": "unnamedWire#21", + "name": "unnamedWire#20", "path": [] }, { @@ -682,7 +670,7 @@ "compName": "nor12#0", "pinName": "D" }, - "name": "unnamedWire#22", + "name": "unnamedWire#21", "path": [] }, { @@ -694,7 +682,7 @@ "compName": "WireCrossPoint#4", "pinName": "" }, - "name": "unnamedWire#23", + "name": "unnamedWire#22", "path": [] }, { @@ -706,7 +694,7 @@ "compName": "Am2910RegCntr#0", "pinName": "D" }, - "name": "unnamedWire#24", + "name": "unnamedWire#23", "path": [] }, { @@ -718,7 +706,7 @@ "compName": "sel4_12#0", "pinName": "I1" }, - "name": "unnamedWire#25", + "name": "unnamedWire#24", "path": [ { "x": 125.0, @@ -740,20 +728,11 @@ "pinName": "_RLD" }, "pin2": { - "compName": "Am2910RegCntr#0", - "pinName": "_RLD" + "compName": "NandGate#3", + "pinName": "A" }, - "name": "unnamedWire#26", - "path": [ - { - "x": 50.0, - "y": 25.0 - }, - { - "x": 50.0, - "y": 15.0 - } - ] + "name": "unnamedWire#25", + "path": [] }, { "pin1": { @@ -764,7 +743,7 @@ "compName": "WireCrossPoint#2", "pinName": "" }, - "name": "unnamedWire#27", + "name": "unnamedWire#26", "path": [ { "x": 175.0, @@ -781,7 +760,7 @@ "compName": "Am2910InstrPLA#0", "pinName": "PASS" }, - "name": "unnamedWire#28", + "name": "unnamedWire#27", "path": [ { "x": 65.0, @@ -806,7 +785,7 @@ "compName": "NandGate#0", "pinName": "A" }, - "name": "unnamedWire#29", + "name": "unnamedWire#28", "path": [] }, { @@ -818,7 +797,7 @@ "compName": "WireCrossPoint#5", "pinName": "" }, - "name": "unnamedWire#30", + "name": "unnamedWire#29", "path": [] }, { @@ -830,7 +809,7 @@ "compName": "NandGate#1", "pinName": "A" }, - "name": "unnamedWire#31", + "name": "unnamedWire#30", "path": [ { "x": 5.0, @@ -847,7 +826,7 @@ "compName": "NandGate#1", "pinName": "B" }, - "name": "unnamedWire#32", + "name": "unnamedWire#31", "path": [] }, { @@ -859,7 +838,7 @@ "compName": "NandGate#0", "pinName": "B" }, - "name": "unnamedWire#33", + "name": "unnamedWire#32", "path": [ { "x": 35.0, @@ -880,7 +859,7 @@ "compName": "_submodelinterface", "pinName": "_FULL" }, - "name": "unnamedWire#34", + "name": "unnamedWire#33", "path": [] }, { @@ -892,7 +871,7 @@ "compName": "dff12#0", "pinName": "C" }, - "name": "unnamedWire#35", + "name": "unnamedWire#34", "path": [ { "x": 240.0, @@ -909,7 +888,7 @@ "compName": "WireCrossPoint#8", "pinName": "" }, - "name": "unnamedWire#36", + "name": "unnamedWire#35", "path": [] }, { @@ -921,7 +900,7 @@ "compName": "Am2910SP#0", "pinName": "C" }, - "name": "unnamedWire#37", + "name": "unnamedWire#36", "path": [] }, { @@ -933,7 +912,7 @@ "compName": "WireCrossPoint#6", "pinName": "" }, - "name": "unnamedWire#38", + "name": "unnamedWire#37", "path": [ { "x": 240.0, @@ -950,7 +929,7 @@ "compName": "Am2910RegCntr#0", "pinName": "C" }, - "name": "unnamedWire#39", + "name": "unnamedWire#38", "path": [] }, { @@ -962,7 +941,7 @@ "compName": "WireCrossPoint#7", "pinName": "" }, - "name": "unnamedWire#40", + "name": "unnamedWire#39", "path": [] }, { @@ -974,7 +953,7 @@ "compName": "_submodelinterface", "pinName": "CI" }, - "name": "unnamedWire#41", + "name": "unnamedWire#40", "path": [ { "x": 250.0, @@ -1003,7 +982,7 @@ "compName": "_submodelinterface", "pinName": "_PL" }, - "name": "unnamedWire#42", + "name": "unnamedWire#41", "path": [ { "x": 45.0, @@ -1024,7 +1003,7 @@ "compName": "_submodelinterface", "pinName": "_MAP" }, - "name": "unnamedWire#43", + "name": "unnamedWire#42", "path": [ { "x": 60.0, @@ -1045,7 +1024,7 @@ "compName": "_submodelinterface", "pinName": "_VECT" }, - "name": "unnamedWire#44", + "name": "unnamedWire#43", "path": [ { "x": 75.0, @@ -1066,7 +1045,7 @@ "compName": "Am2910InstrPLA#0", "pinName": "I" }, - "name": "unnamedWire#45", + "name": "unnamedWire#44", "path": [ { "x": 25.0, @@ -1087,7 +1066,7 @@ "compName": "ram5_12#0", "pinName": "C" }, - "name": "unnamedWire#46", + "name": "unnamedWire#45", "path": [] }, { @@ -1099,7 +1078,7 @@ "compName": "_submodelinterface", "pinName": "Y" }, - "name": "unnamedWire#47", + "name": "unnamedWire#46", "path": [] }, { @@ -1111,7 +1090,7 @@ "compName": "WireCrossPoint#9", "pinName": "" }, - "name": "unnamedWire#48", + "name": "unnamedWire#47", "path": [] }, { @@ -1123,7 +1102,7 @@ "compName": "NandGate#2", "pinName": "B" }, - "name": "unnamedWire#49", + "name": "unnamedWire#48", "path": [] }, { @@ -1135,7 +1114,7 @@ "compName": "WireCrossPoint#9", "pinName": "" }, - "name": "unnamedWire#50", + "name": "unnamedWire#49", "path": [ { "x": 200.0, @@ -1152,7 +1131,7 @@ "compName": "NandGate#2", "pinName": "Y" }, - "name": "unnamedWire#51", + "name": "unnamedWire#50", "path": [ { "x": 230.0, @@ -1163,6 +1142,47 @@ "y": 210.0 } ] + }, + { + "pin1": { + "compName": "Am2910InstrPLA#0", + "pinName": "_RLD" + }, + "pin2": { + "compName": "NandGate#3", + "pinName": "B" + }, + "name": "unnamedWire#51", + "path": [ + { + "x": 95.0, + "y": 105.0 + }, + { + "x": 95.0, + "y": 95.0 + }, + { + "x": 85.0, + "y": 95.0 + }, + { + "x": 85.0, + "y": 35.0 + } + ] + }, + { + "pin1": { + "compName": "NandGate#3", + "pinName": "Y" + }, + "pin2": { + "compName": "Am2910RegCntr#0", + "pinName": "LD" + }, + "name": "unnamedWire#52", + "path": [] } ], "version": "0.1.1" diff --git a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json index 22ea72f4..862805a2 100644 --- a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json +++ b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json @@ -38,15 +38,6 @@ "logicWidth": 1, "usage": "OUTPUT" }, - { - "location": { - "x": 60.0, - "y": 5.0 - }, - "name": "RLD", - "logicWidth": 1, - "usage": "OUTPUT" - }, { "location": { "x": 60.0, @@ -119,6 +110,15 @@ "logicWidth": 1, "usage": "OUTPUT" }, + { + "location": { + "x": 60.0, + "y": 5.0 + }, + "name": "_RLD", + "logicWidth": 1, + "usage": "OUTPUT" + }, { "location": { "x": 45.0, @@ -762,6 +762,15 @@ }, "params": 1 }, + { + "id": "NandGate", + "name": "NandGate#70", + "pos": { + "x": 390.0, + "y": 40.0 + }, + "params": 1 + }, { "id": "Splitter", "name": "Splitter#0", @@ -1706,15 +1715,15 @@ "name": "and#9", "pos": { "x": 355.0, - "y": 45.0 + "y": 40.0 } }, { "id": "and", "name": "and#10", "pos": { - "x": 390.0, - "y": 45.0 + "x": 385.0, + "y": 430.0 } }, { @@ -1772,14 +1781,6 @@ "x": 415.0, "y": 345.0 } - }, - { - "id": "and", - "name": "and#18", - "pos": { - "x": 385.0, - "y": 430.0 - } } ], "wires": [ @@ -2724,12 +2725,12 @@ }, { "pin1": { - "compName": "and#10", + "compName": "NandGate#70", "pinName": "Y" }, "pin2": { "compName": "_submodelinterface", - "pinName": "RLD" + "pinName": "_RLD" }, "name": "unnamedWire#64", "path": [] @@ -2752,7 +2753,7 @@ "pinName": "Y" }, "pin2": { - "compName": "and#10", + "compName": "NandGate#70", "pinName": "A" }, "name": "unnamedWire#66", @@ -3263,7 +3264,7 @@ }, { "x": 350.0, - "y": 50.0 + "y": 45.0 } ] }, @@ -4200,7 +4201,7 @@ }, { "pin1": { - "compName": "and#10", + "compName": "NandGate#70", "pinName": "B" }, "pin2": { @@ -4211,7 +4212,7 @@ "path": [ { "x": 385.0, - "y": 60.0 + "y": 55.0 }, { "x": 385.0, @@ -5307,7 +5308,7 @@ "pinName": "" }, "pin2": { - "compName": "and#18", + "compName": "and#10", "pinName": "A" }, "name": "unnamedWire#227", @@ -5319,7 +5320,7 @@ "pinName": "" }, "pin2": { - "compName": "and#18", + "compName": "and#10", "pinName": "B" }, "name": "unnamedWire#228", @@ -5327,7 +5328,7 @@ }, { "pin1": { - "compName": "and#18", + "compName": "and#10", "pinName": "Y" }, "pin2": { @@ -5654,7 +5655,7 @@ "path": [ { "x": 350.0, - "y": 60.0 + "y": 55.0 } ] }, diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/ModelAm2910RegCntr.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/ModelAm2910RegCntr.java index baa19bf3..d7b32f01 100644 --- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/ModelAm2910RegCntr.java +++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/am2900/components/am2910/ModelAm2910RegCntr.java @@ -25,7 +25,6 @@ public class ModelAm2910RegCntr extends SimpleRectangularHardcodedModelComponent super(model, "Am2910RegCntr", name, "Register/\nCounter", false); setSize(40, 40); addPin(new Pin(model, this, "D", 12, PinUsage.INPUT, 20, 0), Position.BOTTOM); - addPin(new Pin(model, this, "_RLD", 1, PinUsage.INPUT, 0, 5), Position.RIGHT); addPin(new Pin(model, this, "LD", 1, PinUsage.INPUT, 0, 20), Position.RIGHT); addPin(new Pin(model, this, "DEC", 1, PinUsage.INPUT, 0, 30), Position.RIGHT); addPin(new Pin(model, this, "C", 1, PinUsage.INPUT, 40, 20), Position.LEFT); @@ -40,7 +39,6 @@ public class ModelAm2910RegCntr extends SimpleRectangularHardcodedModelComponent Bit[] QC = castAndInitState(lastState); ReadEnd D = readEnds.get("D"); - ReadEnd _RLD = readEnds.get("_RLD"); ReadEnd LD = readEnds.get("LD"); ReadEnd DEC = readEnds.get("DEC"); ReadEnd C = readEnds.get("C"); @@ -52,7 +50,8 @@ public class ModelAm2910RegCntr extends SimpleRectangularHardcodedModelComponent // TODO handle U/X/Z if (oldCVal == ZERO && CVal == ONE) { - if (LD.getValue() == ONE || _RLD.getValue() == ZERO) +// if (LD.getValue() == ONE || _RLD.getValue() == ZERO) + if (LD.getValue() == ONE) System.arraycopy(D.getValues().getBits(), 0, QC, 0, 12); else if (DEC.getValue() == ONE) {