From: Daniel Kirschten <daniel.kirschten@gmx.de>
Date: Sun, 5 Jan 2020 23:13:31 +0000 (+0100)
Subject: VerilogExporter: Components are now named
X-Git-Url: https://mograsim.net/gitweb/?p=Mograsim.git;a=commitdiff_plain;h=dfeebad528797afaf1889ba0bd81a248fba00420

VerilogExporter: Components are now named
---

diff --git a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
index e5c24435..70907f14 100644
--- a/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
+++ b/plugins/net.mograsim.logic.model.am2900/src/net/mograsim/logic/model/examples/VerilogExporter.java
@@ -423,6 +423,9 @@ public class VerilogExporter
 			result.append(COMPONENT_PREFIX);
 			String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
 			result.append(sanitizeVerilog(subcomponentID + paramsString));
+			result.append(' ');
+			// abuse the pinIdentifierGenerator for making these unique
+			result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
 			result.append(" (");
 			for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
 			{