From 38736260ce55efa03e8abd5b1a13bece20172cb4 Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Mon, 14 Dec 2020 03:33:08 +0100 Subject: [PATCH] Fixed a bug regarding internally connected pins --- .../SubmodelComponentConverter.java | 43 +++++++++---------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/components/SubmodelComponentConverter.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/components/SubmodelComponentConverter.java index 0220aaa5..c86fa945 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/components/SubmodelComponentConverter.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/components/SubmodelComponentConverter.java @@ -135,30 +135,29 @@ public class SubmodelComponentConverter implements ComponentConverter arguments = new ArrayList<>(parameterCount); for (int i = 0; i < parameterCount; i++) arguments.add(null); - for (Pin pin : subcomponent.getPins().values()) - for (int bit = 0; bit < pin.logicWidth; bit++) + for (Set connectedGroup : subcomponentMapping.getInternallyConnectedPins()) + { + PinNameBit pinnamebit = connectedGroup.iterator().next(); + String pinBaseName = subcomponentVerilogName + "_" + pinnamebit.getName() + "_" + pinnamebit.getBit(); + PinBit root = connectedPins.find(pinnamebit.toPinBit(subcomponent)); + Wire outSignal = new Wire(idGen.generateID(pinBaseName), 2); + statements.add(new WireDeclaration(outSignal)); + Expression preExpr = currentPreExprs.put(root, new SignalReference(outSignal)); + Expression outExpr = new SignalReference(outSignal); + Expression resExpr = resExprs.get(root); + if (resExpr == null) { - PinBit pinbit = new PinBit(pin, bit); - PinBit root = connectedPins.find(pinbit); - Wire outSignal = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit), 2); - statements.add(new WireDeclaration(outSignal)); - Expression preExpr = currentPreExprs.put(root, new SignalReference(outSignal)); - Expression outExpr = new SignalReference(outSignal); - Expression resExpr = resExprs.get(root); - if (resExpr == null) - { - preExpr = new Constant(BitVector.of(Bit.ZERO, 2)); - Wire resWire = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit + "_res"), 2); - resExpr = new SignalReference(resWire); - statements.add(new WireDeclaration(resWire)); - finalOutSignals.put(root, resWire); - resExprs.put(root, resExpr); - } - PinNameBit pinnamebit = pinbit.toPinNameBit(); - arguments.set(subcomponentMapping.getPrePinMapping().get(pinnamebit).getPortIndex(), preExpr); - arguments.set(subcomponentMapping.getOutPinMapping().get(pinnamebit).getPortIndex(), outExpr); - arguments.set(subcomponentMapping.getResPinMapping().get(pinnamebit).getPortIndex(), resExpr); + preExpr = new Constant(BitVector.of(Bit.ZERO, 2)); + Wire resWire = new Wire(idGen.generateID(pinBaseName + "_res"), 2); + resExpr = new SignalReference(resWire); + statements.add(new WireDeclaration(resWire)); + finalOutSignals.put(root, resWire); + resExprs.put(root, resExpr); } + arguments.set(subcomponentMapping.getPrePinMapping().get(pinnamebit).getPortIndex(), preExpr); + arguments.set(subcomponentMapping.getOutPinMapping().get(pinnamebit).getPortIndex(), outExpr); + arguments.set(subcomponentMapping.getResPinMapping().get(pinnamebit).getPortIndex(), resExpr); + } statements .add(new ComponentReference(subcomponentVerilogName, subcomponentMapping.getVerilogComponentDeclaration(), arguments)); } -- 2.17.1