From c6087221c312e76ad07cf75da61c735278ab8634 Mon Sep 17 00:00:00 2001 From: Daniel Kirschten Date: Sun, 13 Dec 2020 19:32:15 +0100 Subject: [PATCH] Improvements in the ModelComponentToVerilogConverter: +Internally connected pins are now supported +WireCrossPoints are now supported (without external definitions) Refined the Verilog model --- ...tToVerilogComponentDeclarationMapping.java | 20 +++ .../ModelComponentToVerilogConverter.java | 122 ++++++++++-------- .../model/verilog/converter/PinNameBit.java | 13 ++ .../converter/VerilogEmulatedModelPin.java | 4 +- .../model/VerilogComponentDeclaration.java | 2 + .../model/VerilogComponentImplementation.java | 102 ++++----------- .../verilog/model/expressions/Expression.java | 24 ++++ .../model/expressions/SignalReference.java | 29 +++++ .../verilog/model/{ => signals}/Constant.java | 2 +- .../verilog/model/{ => signals}/IOPort.java | 2 +- .../verilog/model/{ => signals}/Input.java | 2 +- .../model/{ => signals}/NamedSignal.java | 2 +- .../verilog/model/{ => signals}/Output.java | 2 +- .../verilog/model/{ => signals}/Signal.java | 2 +- .../verilog/model/{ => signals}/Wire.java | 2 +- .../model/{ => statements}/Assign.java | 47 +++++-- .../{ => statements}/ComponentReference.java | 28 +++- .../verilog/model/statements/Statement.java | 16 +++ .../model/statements/WireDeclaration.java | 80 ++++++++++++ .../model/verilog/utils/CollectionsUtils.java | 19 +++ .../IdentifierGenerator.java | 2 +- .../verilog/{helper => utils}/UnionFind.java | 32 ++++- .../model/verilog/examples/ExportAm2900.java | 11 +- 23 files changed, 406 insertions(+), 159 deletions(-) create mode 100644 plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/Expression.java create mode 100644 plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/SignalReference.java rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/Constant.java (95%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/IOPort.java (77%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/Input.java (80%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/NamedSignal.java (94%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/Output.java (80%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/Signal.java (95%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => signals}/Wire.java (80%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => statements}/Assign.java (59%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/{ => statements}/ComponentReference.java (82%) create mode 100644 plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Statement.java create mode 100644 plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/WireDeclaration.java create mode 100644 plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/CollectionsUtils.java rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/{helper => utils}/IdentifierGenerator.java (95%) rename plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/{helper => utils}/UnionFind.java (64%) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java index 808ac51f..b05e152b 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogComponentDeclarationMapping.java @@ -7,6 +7,7 @@ import java.util.List; import java.util.Map; import java.util.Objects; import java.util.Set; +import java.util.stream.Collectors; import com.google.gson.JsonElement; @@ -20,6 +21,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping private final VerilogComponentDeclaration verilogComponentDeclaration; private final Set pinMapping; + private final Set> internallyConnectedPins; private final Map prePinMapping; private final Map outPinMapping; private final Map resPinMapping; @@ -35,6 +37,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping this.reversePinMapping = checkAndCalculateReversePinMapping(); + this.internallyConnectedPins = calculateInternallyConnectedPins(); this.prePinMapping = filterPinMapping(Type.PRE); this.outPinMapping = filterPinMapping(Type.OUT); this.resPinMapping = filterPinMapping(Type.RES); @@ -67,6 +70,11 @@ public class ModelComponentToVerilogComponentDeclarationMapping return reverseMapping; } + private Set> calculateInternallyConnectedPins() + { + return pinMapping.stream().map(VerilogEmulatedModelPin::getPinbits).collect(Collectors.toUnmodifiableSet()); + } + private Map filterPinMapping(Type filteredType) { Map result = new HashMap<>(); @@ -92,6 +100,11 @@ public class ModelComponentToVerilogComponentDeclarationMapping return verilogComponentDeclaration; } + public Set> getInternallyConnectedPins() + { + return internallyConnectedPins; + } + public Set getPinMapping() { return pinMapping; @@ -123,6 +136,7 @@ public class ModelComponentToVerilogComponentDeclarationMapping final int prime = 31; int result = 1; result = prime * result + ((modelComponentID == null) ? 0 : modelComponentID.hashCode()); + result = prime * result + ((modelComponentParams == null) ? 0 : modelComponentParams.hashCode()); result = prime * result + ((pinMapping == null) ? 0 : pinMapping.hashCode()); result = prime * result + ((verilogComponentDeclaration == null) ? 0 : verilogComponentDeclaration.hashCode()); return result; @@ -144,6 +158,12 @@ public class ModelComponentToVerilogComponentDeclarationMapping return false; } else if (!modelComponentID.equals(other.modelComponentID)) return false; + if (modelComponentParams == null) + { + if (other.modelComponentParams != null) + return false; + } else if (!modelComponentParams.equals(other.modelComponentParams)) + return false; if (pinMapping == null) { if (other.pinMapping != null) diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java index b7e87723..673018ed 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/ModelComponentToVerilogConverter.java @@ -20,22 +20,26 @@ import net.mograsim.logic.model.model.components.ModelComponent; import net.mograsim.logic.model.model.components.atomic.ModelSplitter; import net.mograsim.logic.model.model.components.submodels.SubmodelComponent; import net.mograsim.logic.model.model.wires.ModelWire; +import net.mograsim.logic.model.model.wires.ModelWireCrossPoint; import net.mograsim.logic.model.model.wires.Pin; import net.mograsim.logic.model.serializing.IdentifyParams; import net.mograsim.logic.model.verilog.converter.VerilogEmulatedModelPin.Type; -import net.mograsim.logic.model.verilog.helper.IdentifierGenerator; -import net.mograsim.logic.model.verilog.helper.UnionFind; -import net.mograsim.logic.model.verilog.model.Assign; -import net.mograsim.logic.model.verilog.model.ComponentReference; -import net.mograsim.logic.model.verilog.model.Constant; -import net.mograsim.logic.model.verilog.model.IOPort; -import net.mograsim.logic.model.verilog.model.Input; -import net.mograsim.logic.model.verilog.model.NamedSignal; -import net.mograsim.logic.model.verilog.model.Output; -import net.mograsim.logic.model.verilog.model.Signal; import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration; import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation; -import net.mograsim.logic.model.verilog.model.Wire; +import net.mograsim.logic.model.verilog.model.expressions.SignalReference; +import net.mograsim.logic.model.verilog.model.signals.Constant; +import net.mograsim.logic.model.verilog.model.signals.IOPort; +import net.mograsim.logic.model.verilog.model.signals.Input; +import net.mograsim.logic.model.verilog.model.signals.NamedSignal; +import net.mograsim.logic.model.verilog.model.signals.Output; +import net.mograsim.logic.model.verilog.model.signals.Signal; +import net.mograsim.logic.model.verilog.model.signals.Wire; +import net.mograsim.logic.model.verilog.model.statements.Assign; +import net.mograsim.logic.model.verilog.model.statements.ComponentReference; +import net.mograsim.logic.model.verilog.model.statements.Statement; +import net.mograsim.logic.model.verilog.model.statements.WireDeclaration; +import net.mograsim.logic.model.verilog.utils.IdentifierGenerator; +import net.mograsim.logic.model.verilog.utils.UnionFind; public class ModelComponentToVerilogConverter { @@ -60,30 +64,42 @@ public class ModelComponentToVerilogConverter private void convert(ModelComponent modelComponent) { + // these are handled elsewhere + if (modelComponent instanceof ModelSplitter || modelComponent instanceof ModelWireCrossPoint) + return; + String modelID = modelComponent.getIDForSerializing(new IdentifyParams()); JsonElement params = modelComponent.getParamsForSerializingJSON(new IdentifyParams()); if (componentMappingsPerModelIDPerParams.getOrDefault(modelID, Map.of()).containsKey(params)) // we already converted that component, or it was specified externally return; - if (!(modelComponent instanceof SubmodelComponent)) + String verilogID = verilogComponentIDGen.generateID(verilogComponentIDPrefix + modelID + (params.isJsonNull() ? "" : "_" + params)); + + // TODO don't rely on instanceof + if (modelComponent instanceof SubmodelComponent) + convertSubmodelComponent((SubmodelComponent) modelComponent, modelID, params, verilogID); + else throw new IllegalArgumentException( "Can only convert SubmodelComponents, tried to convert " + modelID + " with params " + params); - SubmodelComponent modelComponentC = (SubmodelComponent) modelComponent; + } + + private void convertSubmodelComponent(SubmodelComponent modelComponent, String modelID, JsonElement params, String verilogID) + { + for (ModelComponent subcomponent : modelComponent.submodel.getComponentsByName().values()) + if (!subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME)) + convert(subcomponent); - UnionFind connectedPins = findConnectedPins(modelComponentC); + UnionFind connectedPins = findConnectedPins(modelComponent); - ModelComponentToVerilogComponentDeclarationMapping mapping = mapDeclaration(modelComponentC, connectedPins, modelID, params); + ModelComponentToVerilogComponentDeclarationMapping mapping = mapDeclaration(modelComponent, connectedPins, modelID, params, + verilogID); componentMappingsPerModelIDPerParams.computeIfAbsent(modelID, i -> new HashMap<>()).put(params, mapping); - for (ModelComponent subcomponent : modelComponentC.submodel.getComponentsByName().values()) - if (!(subcomponent instanceof ModelSplitter) && !subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME)) - convert(subcomponent); - - verilogComponents.add(mapImplementation(modelComponentC, connectedPins, mapping)); + verilogComponents.add(mapImplementation(modelComponent, connectedPins, mapping)); } - private static UnionFind findConnectedPins(SubmodelComponent modelComponent) + private UnionFind findConnectedPins(SubmodelComponent modelComponent) { UnionFind connectedPins = new UnionFind<>(); for (ModelWire w : modelComponent.submodel.getWiresByName().values()) @@ -96,15 +112,19 @@ public class ModelComponentToVerilogConverter ModelSplitter splitter = (ModelSplitter) subcomponent; for (int bit = 0; bit < splitter.logicWidth; bit++) connectedPins.union(new PinBit(splitter.getInputPin(), bit), new PinBit(splitter.getOutputPin(bit), 0)); + } else if (!(subcomponent instanceof ModelWireCrossPoint) + && !subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME)) + { + ModelComponentToVerilogComponentDeclarationMapping subcomponentMapping = getComponentMapping(subcomponent); + for (Set connected : subcomponentMapping.getInternallyConnectedPins()) + connectedPins.unionAll(connected.stream().map(p -> p.toPinBit(subcomponent)).collect(Collectors.toList())); } - // TODO connected pins of subcomponents - return connectedPins; } - private ModelComponentToVerilogComponentDeclarationMapping mapDeclaration(SubmodelComponent modelComponent, - UnionFind connectedPins, String modelID, JsonElement params) + private static ModelComponentToVerilogComponentDeclarationMapping mapDeclaration(SubmodelComponent modelComponent, + UnionFind connectedPins, String modelID, JsonElement params, String verilogID) { // TODO this is probably slow Map representantMapping = new HashMap<>(); @@ -117,8 +137,7 @@ public class ModelComponentToVerilogConverter connectedPinsByName.union(pinnamebit, representative); } - return generateCanonicalDeclarationMapping(modelComponent, connectedPinsByName, modelID, params, - verilogComponentIDGen.generateID(verilogComponentIDPrefix + modelID + (params.isJsonNull() ? "" : "_" + params))); + return generateCanonicalDeclarationMapping(modelComponent, connectedPinsByName, modelID, params, verilogID); } public static ModelComponentToVerilogComponentDeclarationMapping generateCanonicalDeclarationMapping(ModelComponent modelComponent, @@ -191,34 +210,28 @@ public class ModelComponentToVerilogConverter Map currentPreSignals = new HashMap<>(); Map finalOutSignals = new HashMap<>(); Map resSignals = new HashMap<>(); - for (Pin submodelPin : modelComponent.getSubmodelPins().values()) - for (int bit = 0; bit < submodelPin.logicWidth; bit++) - { - PinBit pinbit = new PinBit(submodelPin, bit); - PinNameBit pinnamebit = pinbit.toPinNameBit(); - PinBit root = connectedPins.find(pinbit); - resSignals.put(root, declarationMapping.getResPinMapping().get(pinnamebit).getVerilogPort()); - finalOutSignals.put(root, declarationMapping.getOutPinMapping().get(pinnamebit).getVerilogPort()); - Signal prePort = declarationMapping.getPrePinMapping().get(pinnamebit).getVerilogPort(); - Signal previousPrePort = currentPreSignals.put(root, prePort); - assert previousPrePort != null && !previousPrePort.equals(prePort); - } + for (Set connectedPinGroup : declarationMapping.getInternallyConnectedPins()) + { + PinNameBit pinnamebit = connectedPinGroup.iterator().next(); + PinBit root = connectedPins.find(pinnamebit.toSubmodelPinBit(modelComponent)); + resSignals.put(root, declarationMapping.getResPinMapping().get(pinnamebit).getVerilogPort()); + finalOutSignals.put(root, declarationMapping.getOutPinMapping().get(pinnamebit).getVerilogPort()); + currentPreSignals.put(root, declarationMapping.getPrePinMapping().get(pinnamebit).getVerilogPort()); + } IdentifierGenerator idGen = new IdentifierGenerator( declarationMapping.getVerilogComponentDeclaration().getIOPorts().stream().map(IOPort::getName).collect(Collectors.toList()), ModelComponentToVerilogConverter::sanitizeVerilogID); - Set internalWires = new HashSet<>(); - Set subcomponents = new HashSet<>(); + List statements = new ArrayList<>(); for (ModelComponent subcomponent : modelComponent.submodel.getComponentsByName().values()) { // TODO do we really want to use instanceof? - if (subcomponent instanceof ModelSplitter || subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME)) + if (subcomponent instanceof ModelSplitter || subcomponent instanceof ModelWireCrossPoint + || subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME)) continue; String subcomponentVerilogName = idGen.generateID(subcomponent.getName()); - ModelComponentToVerilogComponentDeclarationMapping subcomponentMapping = componentMappingsPerModelIDPerParams - .get(subcomponent.getIDForSerializing(new IdentifyParams())) - .get(subcomponent.getParamsForSerializingJSON(new IdentifyParams())); + ModelComponentToVerilogComponentDeclarationMapping subcomponentMapping = getComponentMapping(subcomponent); int parameterCount = subcomponentMapping.getVerilogComponentDeclaration().getIOPorts().size(); List arguments = new ArrayList<>(parameterCount); for (int i = 0; i < parameterCount; i++) @@ -229,7 +242,7 @@ public class ModelComponentToVerilogConverter PinBit pinbit = new PinBit(pin, bit); PinBit root = connectedPins.find(pinbit); Wire outSignal = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit), 2); - internalWires.add(outSignal); + statements.add(new WireDeclaration(outSignal)); Signal preSignal = currentPreSignals.put(root, outSignal); Signal resSignal = resSignals.get(root); if (resSignal == null) @@ -237,7 +250,7 @@ public class ModelComponentToVerilogConverter preSignal = new Constant(BitVector.of(Bit.ZERO, 2)); Wire resWire = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit + "_res"), 2); resSignal = resWire; - internalWires.add(resWire); + statements.add(new WireDeclaration(resWire)); finalOutSignals.put(root, resWire); resSignals.put(root, resWire); } @@ -246,16 +259,21 @@ public class ModelComponentToVerilogConverter arguments.set(subcomponentMapping.getOutPinMapping().get(pinnamebit).getPortIndex(), outSignal); arguments.set(subcomponentMapping.getResPinMapping().get(pinnamebit).getPortIndex(), resSignal); } - subcomponents + statements .add(new ComponentReference(subcomponentVerilogName, subcomponentMapping.getVerilogComponentDeclaration(), arguments)); } - Set assigns = new HashSet<>(); for (Entry e : finalOutSignals.entrySet()) - assigns.add(new Assign(currentPreSignals.get(e.getKey()), e.getValue())); + statements.add(new Assign(e.getValue(), new SignalReference(currentPreSignals.get(e.getKey())))); + + return new VerilogComponentImplementation(declarationMapping.getVerilogComponentDeclaration(), statements); + } - return new VerilogComponentImplementation(declarationMapping.getVerilogComponentDeclaration(), internalWires, assigns, - subcomponents); + private ModelComponentToVerilogComponentDeclarationMapping getComponentMapping(ModelComponent component) + { + ModelComponentToVerilogComponentDeclarationMapping subcomponentMapping = componentMappingsPerModelIDPerParams + .get(component.getIDForSerializing(new IdentifyParams())).get(component.getParamsForSerializingJSON(new IdentifyParams())); + return subcomponentMapping; } private Set getVerilogComponents() diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/PinNameBit.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/PinNameBit.java index 461aa02d..1a61e08e 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/PinNameBit.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/PinNameBit.java @@ -2,6 +2,9 @@ package net.mograsim.logic.model.verilog.converter; import java.util.Objects; +import net.mograsim.logic.model.model.components.ModelComponent; +import net.mograsim.logic.model.model.components.submodels.SubmodelComponent; + public class PinNameBit { private final String name; @@ -31,6 +34,16 @@ public class PinNameBit return bit; } + public PinBit toPinBit(ModelComponent pinParent) + { + return new PinBit(pinParent.getPin(name), bit); + } + + public PinBit toSubmodelPinBit(SubmodelComponent submodelComponent) + { + return new PinBit(submodelComponent.getSubmodelPin(name), bit); + } + @Override public String toString() { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/VerilogEmulatedModelPin.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/VerilogEmulatedModelPin.java index b27b4853..feccad13 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/VerilogEmulatedModelPin.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/VerilogEmulatedModelPin.java @@ -3,8 +3,8 @@ package net.mograsim.logic.model.verilog.converter; import java.util.Objects; import java.util.Set; -import net.mograsim.logic.model.verilog.model.IOPort; -import net.mograsim.logic.model.verilog.model.Signal; +import net.mograsim.logic.model.verilog.model.signals.IOPort; +import net.mograsim.logic.model.verilog.model.signals.Signal; public class VerilogEmulatedModelPin { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java index bd5b0181..ef6430a7 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentDeclaration.java @@ -5,6 +5,8 @@ import java.util.List; import java.util.Objects; import java.util.Set; +import net.mograsim.logic.model.verilog.model.signals.IOPort; + public class VerilogComponentDeclaration { private final String id; diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java index fe336948..a7a9de29 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/VerilogComponentImplementation.java @@ -1,58 +1,46 @@ package net.mograsim.logic.model.verilog.model; -import java.util.ArrayList; import java.util.HashSet; import java.util.List; import java.util.Objects; import java.util.Set; import java.util.stream.Collectors; -import net.mograsim.logic.model.verilog.model.Signal.Type; +import net.mograsim.logic.model.verilog.model.signals.IOPort; +import net.mograsim.logic.model.verilog.model.signals.Signal; +import net.mograsim.logic.model.verilog.model.statements.Statement; public class VerilogComponentImplementation { private final VerilogComponentDeclaration declaration; - private final Set internalWires; - private final Set assigns; - private final Set subcomponents; + private final List statements; - public VerilogComponentImplementation(VerilogComponentDeclaration declaration, Set internalWires, Set assigns, - Set subcomponents) + public VerilogComponentImplementation(VerilogComponentDeclaration declaration, List statements) { this.declaration = Objects.requireNonNull(declaration); - this.internalWires = Set.copyOf(internalWires); - this.assigns = Set.copyOf(assigns); - this.subcomponents = Set.copyOf(subcomponents); + this.statements = List.copyOf(statements); check(); } private void check() { + Set usedNames = declaration.getIOPorts().stream().map(IOPort::getName).collect(Collectors.toCollection(HashSet::new)); + + for (Statement statement : statements) + for (String definedName : statement.getDefinedNames()) + if (!usedNames.add(definedName)) + throw new IllegalArgumentException("Name occurs twice: " + definedName); + Set allSignals = new HashSet<>(); allSignals.addAll(declaration.getIOPorts()); - allSignals.addAll(internalWires); + statements.stream().map(Statement::getDefinedSignals).forEach(allSignals::addAll); - Set usedNames = declaration.getIOPorts().stream().map(IOPort::getName).collect(Collectors.toCollection(HashSet::new)); - - for (Wire wire : internalWires) - if (!usedNames.add(wire.getName())) - throw new IllegalArgumentException("Name occurs twice: " + wire.getName()); - - for (Assign assign : assigns) - if (!allSignals.contains(assign.getSource()) || !allSignals.contains(assign.getTarget())) - throw new IllegalArgumentException("Referenced an unknown signal: " + assign.getSource()); - - for (ComponentReference subcomponent : subcomponents) - if (!usedNames.add(subcomponent.getName())) - throw new IllegalArgumentException("Name occurs twice: " + subcomponent.getName()); - else if (!subcomponent.getArguments().stream().filter(s -> s.getType() != Type.CONSTANT).allMatch(allSignals::contains)) - { - List unknownSignals = new ArrayList<>(subcomponent.getArguments()); - unknownSignals.removeAll(allSignals); - // we know this list contains at least one element - throw new IllegalArgumentException("Assigning a signal not in the component: " + unknownSignals.get(0)); - } + // do two passes, a signal may be referenced before it is defined + for (Statement statement : statements) + if (!allSignals.containsAll(statement.getReferencedSignals())) + throw new IllegalArgumentException("Referenced an unknown signal: " + + statement.getReferencedSignals().stream().filter(s -> !allSignals.contains(s)).findAny().get()); } public VerilogComponentDeclaration getDeclaration() @@ -60,19 +48,9 @@ public class VerilogComponentImplementation return declaration; } - public Set getInternalWires() - { - return internalWires; - } - - public Set getAssigns() - { - return assigns; - } - - public Set getSubcomponents() + public List getStatements() { - return subcomponents; + return statements; } public String toVerilogCode() @@ -83,19 +61,9 @@ public class VerilogComponentImplementation sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")"))); sb.append(";\n\n"); - for (Wire wire : internalWires) - sb.append(wire.toDeclarationVerilogCode() + "\n"); - if (!internalWires.isEmpty()) - sb.append("\n"); - - for (Assign assign : assigns) - sb.append(assign.toVerilogCode() + "\n"); - if (!assigns.isEmpty()) - sb.append("\n"); - - for (ComponentReference subcomponent : subcomponents) - sb.append(subcomponent.toVerilogCode() + "\n"); - if (!subcomponents.isEmpty()) + for (Statement statement : statements) + sb.append(statement.toVerilogCode() + "\n"); + if (!statements.isEmpty()) sb.append("\n"); sb.append("endmodule\n"); @@ -114,10 +82,8 @@ public class VerilogComponentImplementation { final int prime = 31; int result = 1; - result = prime * result + ((assigns == null) ? 0 : assigns.hashCode()); result = prime * result + ((declaration == null) ? 0 : declaration.hashCode()); - result = prime * result + ((internalWires == null) ? 0 : internalWires.hashCode()); - result = prime * result + ((subcomponents == null) ? 0 : subcomponents.hashCode()); + result = prime * result + ((statements == null) ? 0 : statements.hashCode()); return result; } @@ -131,29 +97,17 @@ public class VerilogComponentImplementation if (getClass() != obj.getClass()) return false; VerilogComponentImplementation other = (VerilogComponentImplementation) obj; - if (assigns == null) - { - if (other.assigns != null) - return false; - } else if (!assigns.equals(other.assigns)) - return false; if (declaration == null) { if (other.declaration != null) return false; } else if (!declaration.equals(other.declaration)) return false; - if (internalWires == null) - { - if (other.internalWires != null) - return false; - } else if (!internalWires.equals(other.internalWires)) - return false; - if (subcomponents == null) + if (statements == null) { - if (other.subcomponents != null) + if (other.statements != null) return false; - } else if (!subcomponents.equals(other.subcomponents)) + } else if (!statements.equals(other.statements)) return false; return true; } diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/Expression.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/Expression.java new file mode 100644 index 00000000..b5fa9b37 --- /dev/null +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/Expression.java @@ -0,0 +1,24 @@ +package net.mograsim.logic.model.verilog.model.expressions; + +import java.util.Set; + +import net.mograsim.logic.model.verilog.model.signals.Signal; + +public abstract class Expression +{ + private final int width; + + public Expression(int width) + { + this.width = width; + } + + public int getWidth() + { + return width; + } + + public abstract String toVerilogCode(); + + public abstract Set getReferencedSignals(); +} diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/SignalReference.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/SignalReference.java new file mode 100644 index 00000000..7f553b95 --- /dev/null +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/expressions/SignalReference.java @@ -0,0 +1,29 @@ +package net.mograsim.logic.model.verilog.model.expressions; + +import java.util.Objects; +import java.util.Set; + +import net.mograsim.logic.model.verilog.model.signals.Signal; + +public class SignalReference extends Expression +{ + private final Signal referencedSignal; + + public SignalReference(Signal referencedSignal) + { + super(referencedSignal.getWidth()); + this.referencedSignal = Objects.requireNonNull(referencedSignal); + } + + @Override + public String toVerilogCode() + { + return referencedSignal.toReferenceVerilogCode(); + } + + @Override + public Set getReferencedSignals() + { + return Set.of(referencedSignal); + } +} diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Constant.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Constant.java similarity index 95% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Constant.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Constant.java index 8820d391..46150b9f 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Constant.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Constant.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; import net.mograsim.logic.core.types.BitVector; diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/IOPort.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/IOPort.java similarity index 77% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/IOPort.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/IOPort.java index af9b9408..7d573bb1 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/IOPort.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/IOPort.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; public abstract class IOPort extends NamedSignal { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Input.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java similarity index 80% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Input.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java index d3393278..f80f8085 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Input.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Input.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; public class Input extends IOPort { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/NamedSignal.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/NamedSignal.java similarity index 94% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/NamedSignal.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/NamedSignal.java index 531cd6d0..9fae34b6 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/NamedSignal.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/NamedSignal.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; import java.util.Objects; diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Output.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java similarity index 80% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Output.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java index fc8c704d..0cea00b7 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Output.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Output.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; public class Output extends IOPort { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Signal.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Signal.java similarity index 95% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Signal.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Signal.java index 44f72497..e825cede 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Signal.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Signal.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; import java.util.Objects; diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Wire.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java similarity index 80% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Wire.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java index 31e51fb7..b6d331cc 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Wire.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/signals/Wire.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.signals; public class Wire extends NamedSignal { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Assign.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java similarity index 59% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Assign.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java index 1c58dc6e..e6036f04 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/Assign.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Assign.java @@ -1,16 +1,22 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.statements; import java.util.Objects; +import java.util.Set; -public class Assign +import net.mograsim.logic.model.verilog.model.expressions.Expression; +import net.mograsim.logic.model.verilog.model.signals.NamedSignal; +import net.mograsim.logic.model.verilog.model.signals.Signal; +import net.mograsim.logic.model.verilog.utils.CollectionsUtils; + +public class Assign extends Statement { - private final Signal source; private final NamedSignal target; + private final Expression source; - public Assign(Signal source, NamedSignal target) + public Assign(NamedSignal target, Expression source) { - this.source = Objects.requireNonNull(source); this.target = Objects.requireNonNull(target); + this.source = Objects.requireNonNull(source); check(); } @@ -21,25 +27,44 @@ public class Assign throw new IllegalArgumentException("Signal widthes don't match"); } - public Signal getSource() + public Signal getTarget() { - return source; + return target; } - public Signal getTarget() + public Expression getSource() { - return target; + return source; } + @Override public String toVerilogCode() { - return "assign " + target.toReferenceVerilogCode() + " = " + source.toReferenceVerilogCode() + ";"; + return "assign " + target.toReferenceVerilogCode() + " = " + source.toVerilogCode() + ";"; + } + + @Override + public Set getDefinedNames() + { + return Set.of(); + } + + @Override + public Set getDefinedSignals() + { + return Set.of(); + } + + @Override + public Set getReferencedSignals() + { + return CollectionsUtils.union(Set.of(target), source.getReferencedSignals()); } @Override public String toString() { - return target.getName() + " = " + source.toReferenceVerilogCode(); + return target.getName() + " = " + source; } @Override diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/ComponentReference.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java similarity index 82% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/ComponentReference.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java index 0ef29aac..f676661a 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/ComponentReference.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/ComponentReference.java @@ -1,10 +1,15 @@ -package net.mograsim.logic.model.verilog.model; +package net.mograsim.logic.model.verilog.model.statements; import java.util.List; import java.util.Objects; +import java.util.Set; import java.util.stream.Collectors; -public class ComponentReference +import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration; +import net.mograsim.logic.model.verilog.model.signals.IOPort; +import net.mograsim.logic.model.verilog.model.signals.Signal; + +public class ComponentReference extends Statement { private final String name; private final VerilogComponentDeclaration referencedComponent; @@ -47,6 +52,7 @@ public class ComponentReference return arguments; } + @Override public String toVerilogCode() { StringBuilder sb = new StringBuilder(); @@ -58,6 +64,24 @@ public class ComponentReference return sb.toString(); } + @Override + public Set getDefinedNames() + { + return Set.of(name); + } + + @Override + public Set getDefinedSignals() + { + return Set.of(); + } + + @Override + public Set getReferencedSignals() + { + return Set.copyOf(arguments); + } + @Override public String toString() { diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Statement.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Statement.java new file mode 100644 index 00000000..2f95ebe7 --- /dev/null +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/Statement.java @@ -0,0 +1,16 @@ +package net.mograsim.logic.model.verilog.model.statements; + +import java.util.Set; + +import net.mograsim.logic.model.verilog.model.signals.Signal; + +public abstract class Statement +{ + public abstract String toVerilogCode(); + + public abstract Set getDefinedNames(); + + public abstract Set getDefinedSignals(); + + public abstract Set getReferencedSignals(); +} diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/WireDeclaration.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/WireDeclaration.java new file mode 100644 index 00000000..4d949b48 --- /dev/null +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/statements/WireDeclaration.java @@ -0,0 +1,80 @@ +package net.mograsim.logic.model.verilog.model.statements; + +import java.util.Objects; +import java.util.Set; + +import net.mograsim.logic.model.verilog.model.signals.Signal; +import net.mograsim.logic.model.verilog.model.signals.Wire; + +public class WireDeclaration extends Statement +{ + private final Wire wire; + + public WireDeclaration(Wire wire) + { + this.wire = Objects.requireNonNull(wire); + } + + public Wire getWire() + { + return wire; + } + + @Override + public String toVerilogCode() + { + return wire.toDeclarationVerilogCode(); + } + + @Override + public Set getDefinedNames() + { + return Set.of(wire.getName()); + } + + @Override + public Set getDefinedSignals() + { + return Set.of(wire); + } + + @Override + public Set getReferencedSignals() + { + return Set.of(); + } + + @Override + public String toString() + { + return "decl[" + wire.toString() + "]"; + } + + @Override + public int hashCode() + { + final int prime = 31; + int result = 1; + result = prime * result + ((wire == null) ? 0 : wire.hashCode()); + return result; + } + + @Override + public boolean equals(Object obj) + { + if (this == obj) + return true; + if (obj == null) + return false; + if (getClass() != obj.getClass()) + return false; + WireDeclaration other = (WireDeclaration) obj; + if (wire == null) + { + if (other.wire != null) + return false; + } else if (!wire.equals(other.wire)) + return false; + return true; + } +} diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/CollectionsUtils.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/CollectionsUtils.java new file mode 100644 index 00000000..6d118c35 --- /dev/null +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/CollectionsUtils.java @@ -0,0 +1,19 @@ +package net.mograsim.logic.model.verilog.utils; + +import java.util.HashSet; +import java.util.Set; + +public class CollectionsUtils +{ + private CollectionsUtils() + { + } + + public static Set union(Set a, Set b) + { + Set union = new HashSet<>(); + union.addAll(a); + union.addAll(b); + return Set.copyOf(union); + } +} diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/IdentifierGenerator.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/IdentifierGenerator.java similarity index 95% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/IdentifierGenerator.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/IdentifierGenerator.java index b247f25b..b35d8a62 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/IdentifierGenerator.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/IdentifierGenerator.java @@ -1,4 +1,4 @@ -package net.mograsim.logic.model.verilog.helper; +package net.mograsim.logic.model.verilog.utils; import java.util.Collection; import java.util.HashSet; diff --git a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/UnionFind.java b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/UnionFind.java similarity index 64% rename from plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/UnionFind.java rename to plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/UnionFind.java index 1a97ba29..c78f1ee1 100644 --- a/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/helper/UnionFind.java +++ b/plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/utils/UnionFind.java @@ -1,6 +1,8 @@ -package net.mograsim.logic.model.verilog.helper; +package net.mograsim.logic.model.verilog.utils; +import java.util.Collection; import java.util.HashMap; +import java.util.Iterator; import java.util.Map; public class UnionFind @@ -53,6 +55,34 @@ public class UnionFind } } + public E unionAll(Collection es) + { + Iterator it = es.iterator(); + if (!it.hasNext()) + return null; + + UnionFindElement representant = getElement(it.next()); + + while (it.hasNext()) + representant = union(representant, getElement(it.next())); + + return representant.getE(); + } + + public static UnionFindElement unionAll2(Collection> es) + { + Iterator> it = es.iterator(); + if (!it.hasNext()) + return null; + + UnionFindElement representant = it.next(); + + while (it.hasNext()) + representant = union(representant, it.next()); + + return representant; + } + public static class UnionFindElement { private final E e; diff --git a/tests/net.mograsim.logic.model.verilog.tests/src/net/mograsim/logic/model/verilog/examples/ExportAm2900.java b/tests/net.mograsim.logic.model.verilog.tests/src/net/mograsim/logic/model/verilog/examples/ExportAm2900.java index 08712a0d..a2e46d9b 100644 --- a/tests/net.mograsim.logic.model.verilog.tests/src/net/mograsim/logic/model/verilog/examples/ExportAm2900.java +++ b/tests/net.mograsim.logic.model.verilog.tests/src/net/mograsim/logic/model/verilog/examples/ExportAm2900.java @@ -27,15 +27,14 @@ import net.mograsim.logic.model.model.components.atomic.ModelNandGate; import net.mograsim.logic.model.model.components.atomic.ModelTextComponent; import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer; import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer.ModelTriStateBufferParams; -import net.mograsim.logic.model.model.wires.ModelWireCrossPoint; import net.mograsim.logic.model.serializing.IdentifyParams; import net.mograsim.logic.model.serializing.IndirectModelComponentCreator; import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogComponentDeclarationMapping; import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogConverter; -import net.mograsim.logic.model.verilog.helper.UnionFind; -import net.mograsim.logic.model.verilog.model.IOPort; import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration; import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation; +import net.mograsim.logic.model.verilog.model.signals.IOPort; +import net.mograsim.logic.model.verilog.utils.UnionFind; public class ExportAm2900 { @@ -76,12 +75,6 @@ public class ExportAm2900 new ModelTriStateBuffer(model, new ModelTriStateBufferParams(12, Orientation.DOWN)), // new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.LEFT)), // new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.RIGHT_ALT)), // - new ModelWireCrossPoint(model, 1), // - new ModelWireCrossPoint(model, 2), // - new ModelWireCrossPoint(model, 4), // - new ModelWireCrossPoint(model, 9), // - new ModelWireCrossPoint(model, 12), // - new ModelWireCrossPoint(model, 16), // new ModelClock(model, new ModelClockParams(7000, Orientation.RIGHT)), // new ModelTextComponent(model, "A bus"), // new ModelTextComponent(model, "MPM addr"), // -- 2.17.1