Mograsim.git
2019-05-20 Daniel KirschtenMerged SampleERCP into master
2019-05-20 Daniel KirschtenMerged logicui into master
2019-05-20 Daniel KirschtenMerged logic into master
2019-05-20 Christian FemersMerged master_old into master
2019-05-20 Christian FemersExchanged all Bit[] by BitVector, tests work
2019-05-20 Christian FemersIntegrated new types, tests still work, not used yet
2019-05-20 Fabian Stemmlernew WireEnds as in/outputs are now initialized with...
2019-05-20 Fabian StemmlerCleanup
2019-05-20 Fabian StemmlerMerge logic of origin into logic
2019-05-20 Fabian StemmlerWireArray(Input) is now Wire(End); all in-/outputs...
2019-05-19 Christian FemersDid some clean up
2019-05-19 Christian FemersFixed calculations concerning U, tests work now just...
2019-05-19 Christian FemersMade Connector an Component and more useful
2019-05-19 Daniel KirschtenBetter support for U; applied uniform formatting
2019-05-19 Daniel KirschtenMade formatting uniform - commit for SampleERCP
2019-05-19 Daniel KirschtenMade formatting uniform - commit for logic
2019-05-19 Daniel KirschtenMade formatting uniform - commit for logicui
2019-05-18 Christian FemersWireArrayEnd now created with U and GUITest supports U
2019-05-18 Christian FemersSet formatting save action
2019-05-18 Fabian StemmlerAdded project specific format; Default values in WireAr...
2019-05-18 Fabian StemmlerReformatted everything. Eclipse built-in Linewrapping...
2019-05-16 Daniel KirschtenAdjusted delays in RSLatchGUIExample
2019-05-16 Daniel KirschtenFixed a bug causing new timeline events to not be processed
2019-05-16 Daniel KirschtenAdded comments for LogicUI
2019-05-16 Daniel KirschtenLogicUI improvements
2019-05-16 Daniel KirschtenGUIManualSwitch now shows the actual value of the outpu...
2019-05-16 Daniel KirschtenMade RS latch example more similar to GUITest
2019-05-16 Daniel KirschtenWireConnectionPoints are now smaller
2019-05-16 Daniel KirschtenWireConnectionPoints now have the same color as the...
2019-05-16 Daniel KirschtenFixed incorrect symbol for OR and AND gates
2019-05-16 Daniel KirschtenSplitted LogicUI from hardcoded example code
2019-05-16 Daniel KirschtenRemoved drawing of connection points
2019-05-16 Daniel KirschtenRestructured packages
2019-05-15 Daniel KirschtenLogicUI now is able to interactively run a RS latch
2019-05-15 Daniel KirschtenMade GUIWires more colorful
2019-05-15 Daniel KirschtenA GUIWire now can trigger a redraw
2019-05-15 Daniel KirschtenLogicUI actually runs the simulation
2019-05-15 Daniel KirschtenAdded nextEventTime(); added NewEventListeners
2019-05-15 Daniel KirschtenImplemented the RS-Latch-Example
2019-05-15 Daniel KirschtenImplemented GUIOrGate
2019-05-15 Daniel KirschtenMade ManualSwitch non-final to make GUIManualSwitch...
2019-05-15 Daniel KirschtenMoved LogicUI
2019-05-15 Christian FemersAdded 'U' to Bit and made code IEEE 1164 compliant...
2019-05-15 Daniel KirschtenImproved comment for clicked() in BasicGUIComponent
2019-05-15 Daniel KirschtenMore GUIComponents implemented; components can be clicked
2019-05-15 Daniel KirschtenComponents now can be clicked
2019-05-15 Daniel KirschtenAdded getBounds() in BasicGUIComponent
2019-05-15 Daniel KirschtenAdded comments in BasicGUIComponent
2019-05-15 Daniel KirschtenMade ManualSwitch non-final to make GUIManualSwitch...
2019-05-15 Daniel KirschtenFixed dependencies. LogicUI should now work again.
2019-05-15 Daniel KirschtenUpdated to new SWTHelper version. Now LogicUI should...
2019-05-15 Daniel KirschtenImplemented more GUIComponents
2019-05-15 Daniel KirschtenFixed text centering being off 1.75px
2019-05-15 Daniel KirschtenAdjusted GUIMux appearance to other gates
2019-05-15 Daniel KirschtenImplemented GUIAndGate
2019-05-15 Daniel KirschtenMade connection point markers smaller
2019-05-15 Daniel KirschtenImplemented GUINotGate
2019-05-15 Daniel KirschtenImplemented GUISplitter and GUIMerger
2019-05-14 Daniel KirschtenMoved SWTHelper submodule - commit for master
2019-05-14 Daniel KirschtenMoved SWTHelper submodule - commit for logicui
2019-05-14 Daniel KirschtenAdded SampleERCP submodule
2019-05-14 Daniel KirschtenNew inner-project dependency management - commit for...
2019-05-14 Daniel KirschtenNew inner-project dependency management - commit for...
2019-05-14 Daniel KirschtenNew inner-project dependency management - commit for...
2019-05-14 Daniel KirschtenRemoved obsolete era.mi in master branch
2019-05-14 Christian Femersajusted or() behaviour when Z is input
2019-05-14 Christian FemersAdded GUITest, ManualSwitch and one method to Timeline
2019-05-13 Daniel KirschtenRemoved unused import
2019-05-13 Daniel KirschtenRemoved debug code
2019-05-13 Daniel KirschtenFurther improvements in LogicUI:
2019-05-13 Daniel KirschtenImprovements in LogicUI
2019-05-13 Daniel KirschtenCreated first example class
2019-05-13 Daniel KirschtenCreated LogicUI project
2019-05-13 Daniel KirschtenCreated SWTHelper submodule
2019-05-13 Fabian Stemmlerlogic gates and, or and xor now take an arbitrary amoun...
2019-05-12 Fabian Stemmleradded demux; added getAllInputs() and getAllOutputs...
2019-05-12 Fabian Stemmleradded more doc to Timeline; added functionality to Bit
2019-05-11 Christian Femerssample project as-is
2019-05-11 Christian Femersfixed Connector and added some useful methods to WireAr...
2019-05-11 Fabian StemmlerCleaned up ComponentTest.
2019-05-11 Fabian StemmlerRemoved Mapper class.
2019-05-10 Christian FemersUpdate REQUIREMENTS.MD
2019-05-10 Christian FemersEPL-2.0 added
2019-05-10 Fabian StemmlerFixed Merger, Mux, Splitter: onedirectional again....
2019-05-10 Fabian Stemmlerbin deleted and ignored.
2019-05-10 Christian FemersInitial commit
2019-05-10 Christian Femersadded some classes that improve testing experience
2019-05-10 Christian Femersadded some convenience methods that make our lives...
2019-05-10 Daniel KirschtenMerge branch 'wire_array_inputs_update'
2019-05-10 Fabian StemmlerWire concept was changed to accommodate multiple inputs...
2019-05-07 Christian Femersdeleted everything
2019-05-07 Fabian StemmlerAdded era.mi; Project containing provisional simulator...
2019-05-07 Fabian StemmlerAdded era.mi; Project containing provisional simulator...
2019-05-05 Christian FemersUpdate REQUIREMENTS.MD
2019-05-05 Christian FemersUpdate REQUIREMENTS.MD
2019-05-02 Christian FemersUpdate REQUIREMENTS.MD
2019-05-01 Christian FemersUpdate REQUIREMENTS.MD
2019-05-01 Christian FemersI18n
2019-05-01 Christian FemersUpdate REQUIREMENTS.MD
2019-05-01 Christian FemersUpdate REQUIREMENTS.MD
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