mograsim.net Git - Mograsim.git/tree - plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/model/

drwxr-xr-x		..
-rw-r--r--	1562	Assign.java	blob \| history \| raw
-rw-r--r--	2814	ComponentReference.java	blob \| history \| raw
-rw-r--r--	1171	Constant.java	blob \| history \| raw
-rw-r--r--	239	IOPort.java	blob \| history \| raw
-rw-r--r--	282	Input.java	blob \| history \| raw
-rw-r--r--	1037	NamedSignal.java	blob \| history \| raw
-rw-r--r--	286	Output.java	blob \| history \| raw
-rw-r--r--	1134	Signal.java	blob \| history \| raw
-rw-r--r--	1595	VerilogComponentDeclaration.java	blob \| history \| raw
-rw-r--r--	4620	VerilogComponentImplementation.java	blob \| history \| raw
-rw-r--r--	275	Wire.java	blob \| history \| raw