+++ /dev/null
-package net.mograsim.logic.model.examples;
-
-import java.io.File;
-import java.io.IOException;
-import java.io.UncheckedIOException;
-import java.nio.file.Files;
-import java.nio.file.Path;
-import java.nio.file.Paths;
-import java.util.Arrays;
-import java.util.Comparator;
-import java.util.HashMap;
-import java.util.HashSet;
-import java.util.List;
-import java.util.Map;
-import java.util.Map.Entry;
-import java.util.Scanner;
-import java.util.Set;
-import java.util.stream.Collectors;
-
-import com.google.gson.JsonElement;
-import com.google.gson.JsonNull;
-
-import net.mograsim.logic.model.am2900.Am2900Loader;
-import net.mograsim.logic.model.model.LogicModelModifiable;
-import net.mograsim.logic.model.model.components.ModelComponent;
-import net.mograsim.logic.model.model.components.submodels.SubmodelComponent;
-import net.mograsim.logic.model.model.wires.Pin;
-import net.mograsim.logic.model.serializing.IndirectModelComponentCreator;
-import net.mograsim.logic.model.serializing.LogicModelParams.ComponentParams;
-import net.mograsim.logic.model.serializing.LogicModelParams.WireParams;
-import net.mograsim.logic.model.serializing.LogicModelParams.WireParams.PinParams;
-import net.mograsim.logic.model.serializing.SubmodelComponentParams;
-import net.mograsim.logic.model.serializing.SubmodelComponentParams.InterfacePinParams;
-import net.mograsim.logic.model.serializing.SubmodelComponentSerializer;
-
-//TODO clean this mess
-public class VerilogExporter
-{
- private static final String COMPONENT_PREFIX = "mgs_";
-
- public static void main(String[] args) throws IOException
- {
- Am2900Loader.setup();
- try (Scanner sysin = new Scanner(System.in))
- {
- System.out.print("Directory to export Verilog into >");
- Path target = Paths.get(sysin.nextLine());
- if (!Files.exists(target))
- Files.createDirectories(target);
- else if (!Files.isDirectory(target))
- throw new IllegalArgumentException("Target exists and is not a directory");
-
- System.out.print("Component ID to serialize recursively >");
- String rootComponentID = sysin.nextLine();
- {
- if (!Files.exists(target))
- Files.createDirectories(target);
- else if (!Files.isDirectory(target))
- throw new IllegalArgumentException("Target exists and is not a directory");
- Map<String, SubmodelComponentParams> componentsById = readComponentIncludingDependencies(rootComponentID);
- Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID = new HashMap<>();
- Tuple2<Map<String, Map<String, String>>, Map<String, Map<String, Set<String>>>> combinedPinNames = generateCombinedPinNames(
- componentsById, pinIdentifierGeneratorsPerComponentID);
- Map<String, Tuple2<List<String>, List<Integer>>> sortedInterfacePinNamesAndWidthsPerComponentID = generateSortedInterfacePinNamesAndWidthesPerComponentID(
- componentsById, combinedPinNames.e1);
- writeComponentsVerilog(target, componentsById, pinIdentifierGeneratorsPerComponentID,
- sortedInterfacePinNamesAndWidthsPerComponentID, combinedPinNames);
- }
- }
- }
-
- private static Map<String, SubmodelComponentParams> readComponentIncludingDependencies(String rootComponentID)
- {
- Map<String, SubmodelComponentParams> result = new HashMap<>();
- readComponentIncludingDependenciesRecursively(rootComponentID, null, result);
- return result;
- }
-
- private static void readComponentIncludingDependenciesRecursively(String id, JsonElement params,
- Map<String, SubmodelComponentParams> result)
- {
- if (result.containsKey(id))
- return;
-
- ModelComponent component = IndirectModelComponentCreator.createComponent(new LogicModelModifiable(), id, params);
- if (component instanceof SubmodelComponent)
- {
- SubmodelComponentParams componentJson = SubmodelComponentSerializer.serialize((SubmodelComponent) component);
- result.put(id, componentJson);
- for (ComponentParams subcomponentParams : componentJson.submodel.components)
- readComponentIncludingDependenciesRecursively(subcomponentParams.id, subcomponentParams.params, result);
- }
- }
-
- private static Tuple2<Map<String, Map<String, String>>, Map<String, Map<String, Set<String>>>> generateCombinedPinNames(
- Map<String, SubmodelComponentParams> componentsById, Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID)
- {
- Map<String, Map<String, Set<String>>> connectedInnerPinNamesPerComponentID = new HashMap<>();
-
- generateConnectedInnerPins(componentsById, pinIdentifierGeneratorsPerComponentID, connectedInnerPinNamesPerComponentID);
-
- Map<String, Map<String, String>> combinedInterfacePinNamesPerComponentID = new HashMap<>();
-
- for (boolean anyChange = true; anyChange;)
- {
- anyChange = false;
- for (Entry<String, SubmodelComponentParams> e : componentsById.entrySet())
- anyChange |= checkForConnectedPins(e.getKey(), e.getValue(), componentsById, pinIdentifierGeneratorsPerComponentID,
- connectedInnerPinNamesPerComponentID, combinedInterfacePinNamesPerComponentID);
- }
-
- return new Tuple2<>(combinedInterfacePinNamesPerComponentID, connectedInnerPinNamesPerComponentID);
- }
-
- private static boolean checkForConnectedPins(String componentID, SubmodelComponentParams componentJson,
- Map<String, SubmodelComponentParams> componentsById, Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID,
- Map<String, Map<String, Set<String>>> connectedInnerPinNamesPerComponentID,
- Map<String, Map<String, String>> combinedPinNamesPerComponentID)
- {
- PinIdentifierGenerator pinIdentifierGenerator = pinIdentifierGeneratorsPerComponentID.get(componentID);
- Map<String, Set<String>> connectedInnerPinNames = connectedInnerPinNamesPerComponentID.get(componentID);
- Map<String, String> pinNameRemapping = combinedPinNamesPerComponentID.computeIfAbsent(componentID, k ->
- {
- Map<String, String> result = new HashMap<>();
- for (InterfacePinParams pinParams : componentJson.interfacePins)
- result.put(pinParams.name, pinParams.name);
- return result;
- });
-
- for (InterfacePinParams pin1Params : componentJson.interfacePins)
- {
- String pin1Name = pinNameRemapping.get(pin1Params.name);
- Set<String> connectedInnerPinNamesPin1 = connectedInnerPinNames
- .get(pinIdentifierGenerator.getPinID(SubmodelComponent.SUBMODEL_INTERFACE_NAME, pin1Name));
- if (connectedInnerPinNamesPin1 != null)
- for (InterfacePinParams pin2Params : componentJson.interfacePins)
- {
- String pin2Name = pinNameRemapping.get(pin2Params.name);
- String pin2InnerPinName = pinIdentifierGenerator.getPinID(SubmodelComponent.SUBMODEL_INTERFACE_NAME, pin2Name);
- if (connectedInnerPinNamesPin1.contains(pin2InnerPinName) && !pin1Name.equals(pin2Name))
- {
- System.out.println("These pins of component " + componentID + " are connected: " + pin1Name + " and " + pin2Name);
- for (Entry<String, String> e : pinNameRemapping.entrySet())
- if (e.getValue().equals(pin2Name))
- e.setValue(pin1Name);
- connectPinsInSupercomponents(componentID, pin1Name, pin2Name, componentsById, pinIdentifierGeneratorsPerComponentID,
- connectedInnerPinNamesPerComponentID);
- return true;
- }
- }
- }
- return false;
- }
-
- private static void connectPinsInSupercomponents(String componentID, String pin1Name, String pin2Name,
- Map<String, SubmodelComponentParams> componentsById, Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID,
- Map<String, Map<String, Set<String>>> connectedInnerPinNamesPerComponentID)
- {
- for (Entry<String, SubmodelComponentParams> e : componentsById.entrySet())
- {
- String superComponentID = e.getKey();
- SubmodelComponentParams superComponentJson = e.getValue();
-
- PinIdentifierGenerator pinIdentifierGenerator = pinIdentifierGeneratorsPerComponentID.get(superComponentID);
- Map<String, Set<String>> connectedPinNames = connectedInnerPinNamesPerComponentID.get(superComponentID);
-
- for (ComponentParams subcomponentParams : superComponentJson.submodel.components)
- if (subcomponentParams.id.equals(componentID))
- {
- String pin1ID = pinIdentifierGenerator.getPinID(subcomponentParams.name, pin1Name);
- String pin2ID = pinIdentifierGenerator.getPinID(subcomponentParams.name, pin2Name);
-
- Set<String> connectedPinNamesPin1 = connectedPinNames.get(pin1ID);
- Set<String> connectedPinNamesPin2 = connectedPinNames.get(pin2ID);
-
- if (connectedPinNamesPin2 != null)
- {
- connectedPinNamesPin2.remove(pin2ID);
- if (connectedPinNamesPin1 != null)
- {
- connectedPinNamesPin2.addAll(connectedPinNamesPin1);
- for (String pinNameToRewriteMapping : connectedPinNamesPin1)
- connectedPinNames.put(pinNameToRewriteMapping, connectedPinNamesPin2);
- }
- }
- }
- }
- }
-
- private static void generateConnectedInnerPins(Map<String, SubmodelComponentParams> componentsById,
- Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID,
- Map<String, Map<String, Set<String>>> connectedInnerPinNamesPerComponentID)
- {
- for (Entry<String, SubmodelComponentParams> e : componentsById.entrySet())
- {
- String componentID = e.getKey();
- SubmodelComponentParams componentJson = e.getValue();
-
- PinIdentifierGenerator pinIdentifierGenerator = new PinIdentifierGenerator();
- Map<String, Set<String>> connectedInnerPinNames = new HashMap<>();
- pinIdentifierGeneratorsPerComponentID.put(componentID, pinIdentifierGenerator);
- connectedInnerPinNamesPerComponentID.put(componentID, connectedInnerPinNames);
-
- for (WireParams wireJson : componentJson.submodel.wires)
- {
- String pin1Name = pinIdentifierGenerator.getPinID(wireJson.pin1);
- String pin2Name = pinIdentifierGenerator.getPinID(wireJson.pin2);
-
- Set<String> oldConnectedPins1 = connectedInnerPinNames.get(pin1Name);
- Set<String> oldConnectedPins2 = connectedInnerPinNames.get(pin2Name);
-
- if (oldConnectedPins1 == null)
- oldConnectedPins1 = Set.of(pin1Name);
- if (oldConnectedPins2 == null)
- {
- oldConnectedPins2 = new HashSet<>(Arrays.asList(pin2Name));
- connectedInnerPinNames.put(pin2Name, oldConnectedPins2);
- }
-
- oldConnectedPins2.addAll(oldConnectedPins1);
- for (String pinNameToRewriteMapping : oldConnectedPins1)
- connectedInnerPinNames.put(pinNameToRewriteMapping, oldConnectedPins2);
- }
- }
- }
-
- private static Map<String, Tuple2<List<String>, List<Integer>>> generateSortedInterfacePinNamesAndWidthesPerComponentID(
- Map<String, SubmodelComponentParams> componentsById, Map<String, Map<String, String>> combinedInterfacePinsPerComponentID)
- {
- return combinedInterfacePinsPerComponentID.entrySet().stream().collect(Collectors.toMap(Entry::getKey, e ->
- {
- List<String> names = e.getValue().values().stream().distinct().sorted().collect(Collectors.toList());
- System.out.println("Assuming following order for interface pins of " + e.getKey() + ": " + names);
- Map<String, Integer> widthesPerName = Arrays.stream(componentsById.get(e.getKey()).interfacePins)
- .collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
- List<Integer> widthes = names.stream().map(widthesPerName::get).collect(Collectors.toList());
- return new Tuple2<>(names, widthes);
- }));
- }
-
- private static void writeComponentsVerilog(Path target, Map<String, SubmodelComponentParams> componentsById,
- Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID,
- Map<String, Tuple2<List<String>, List<Integer>>> sortedInterfacePinNamesAndWidthsPerComponentID,
- Tuple2<Map<String, Map<String, String>>, Map<String, Map<String, Set<String>>>> combinedPinNames)
- {
- componentsById.forEach((componentID, componentJson) ->
- {
- try
- {
- String componentPathStr = componentID.replace(File.separator, "_").replace('.', '_');
- Path componentPathWithoutPrefix = target.resolve(componentPathStr + ".v");
- Path componentParent = componentPathWithoutPrefix.getParent();
- String componentName = componentPathWithoutPrefix.getFileName().toString();
- Files.createDirectories(componentParent);
- Files.writeString(componentParent.resolve(COMPONENT_PREFIX + componentName),
- new VerilogExporter(componentID, componentJson, pinIdentifierGeneratorsPerComponentID,
- sortedInterfacePinNamesAndWidthsPerComponentID, combinedPinNames).generateVerilog());
- }
- catch (IOException e)
- {
- throw new UncheckedIOException(e);
- }
- });
- }
-
- private final String componentID;
- private final SubmodelComponentParams componentJson;
-
- private final PinIdentifierGenerator pinIdentifierGenerator;
- private final Map<String, Set<String>> combinedInnerPinNames;
- private final List<String> sortedInterfacePinNames;
- private final Map<String, Tuple2<List<String>, List<Integer>>> sortedInterfacePinNamesAndWidthsPerComponentID;
-
- public VerilogExporter(String componentID, SubmodelComponentParams componentJson,
- Map<String, PinIdentifierGenerator> pinIdentifierGeneratorsPerComponentID,
- Map<String, Tuple2<List<String>, List<Integer>>> sortedInterfacePinNamesAndWidthsPerComponentID,
- Tuple2<Map<String, Map<String, String>>, Map<String, Map<String, Set<String>>>> combinedPinNames)
- {
- this.componentID = componentID;
- this.componentJson = componentJson;
-
- this.pinIdentifierGenerator = pinIdentifierGeneratorsPerComponentID.get(componentID);
- this.combinedInnerPinNames = combinedPinNames.e2.get(componentID);
- this.sortedInterfacePinNames = sortedInterfacePinNamesAndWidthsPerComponentID.get(componentID).e1;
- this.sortedInterfacePinNamesAndWidthsPerComponentID = sortedInterfacePinNamesAndWidthsPerComponentID;
- }
-
- public String generateVerilog()
- {
- StringBuilder result = new StringBuilder();
-
- result.append("module ");
- result.append(COMPONENT_PREFIX);
- result.append(sanitizeVerilog(componentID));
-
- result.append(" (");
- appendInterface(result);
- result.append(");\n\n");
-
- appendComponents(result);
-
- result.append("endmodule\n");
-
- return result.toString();
- }
-
- private void appendInterface(StringBuilder result)
- {
- result.append("input rst, input clk");
- if (!sortedInterfacePinNames.isEmpty())
- {
- Map<String, Integer> logicWidthsPerInterfacePinName = Arrays.stream(componentJson.interfacePins)
- .collect(Collectors.toMap(p -> p.name, p -> p.logicWidth));
- for (int i = 0; i < sortedInterfacePinNames.size(); i++)
- {
- result.append(",\n");
- String interfacePinName = sortedInterfacePinNames.get(i);
- int logicWidth = logicWidthsPerInterfacePinName.get(interfacePinName);
-
- result.append(" input ");
- appendLogicWidth(result, logicWidth);
- result.append(sanitizeVerilog(interfacePinName));
- result.append("_pre, output ");
- appendLogicWidth(result, logicWidth);
- result.append(sanitizeVerilog(interfacePinName));
- result.append("_out, input ");
- appendLogicWidth(result, logicWidth);
- result.append(sanitizeVerilog(interfacePinName));
- result.append("_res");
- }
- result.append('\n');
- }
- }
-
- private void appendComponents(StringBuilder result)
- {
- Map<Set<String>, String> currentWireNamePerCombinedInnerPinNames = new HashMap<>();
- Map<Set<String>, String> resultWireNamePerCombinedInnerPinNames = new HashMap<>();
- for (Set<String> s : combinedInnerPinNames.values())
- {
- currentWireNamePerCombinedInnerPinNames.put(s, "2'b00");
-
- String anyInnerPinName = s.iterator().next();
- // abuse the pinIdentifierGenerator for generating an unique wire name
- String uniqueWireName = pinIdentifierGenerator.getPinID(anyInnerPinName, "res");
- resultWireNamePerCombinedInnerPinNames.put(s, uniqueWireName);
- }
- for (String interfacePinName : sortedInterfacePinNames)
- {
- String innerPinID = pinIdentifierGenerator.getPinID(SubmodelComponent.SUBMODEL_INTERFACE_NAME, interfacePinName);
- Set<String> connectedPins = combinedInnerPinNames.get(innerPinID);
- currentWireNamePerCombinedInnerPinNames.put(connectedPins, interfacePinName + "_pre");
- resultWireNamePerCombinedInnerPinNames.put(connectedPins, interfacePinName + "_res");
- }
-
- for (ComponentParams subcomponentParams : componentJson.submodel.components)
- appendComponent(result, currentWireNamePerCombinedInnerPinNames, resultWireNamePerCombinedInnerPinNames, subcomponentParams);
-
- for (String interfacePinName : sortedInterfacePinNames)
- {
- String innerPinID = pinIdentifierGenerator.getPinID(SubmodelComponent.SUBMODEL_INTERFACE_NAME, interfacePinName);
- Set<String> connectedPins = combinedInnerPinNames.get(innerPinID);
- String lastWireName = currentWireNamePerCombinedInnerPinNames.remove(connectedPins);
-
- result.append("assign ");
- result.append(sanitizeVerilog(interfacePinName));
- result.append("_out");
- result.append(" = ");
- result.append(sanitizeVerilog(lastWireName));
- result.append(";\n");
- }
- for (Set<String> s : currentWireNamePerCombinedInnerPinNames.keySet())
- {
- String lastWireName = currentWireNamePerCombinedInnerPinNames.get(s);
- String resultWireName = resultWireNamePerCombinedInnerPinNames.get(s);
-
- result.append("wire ");
- int logicWidth = -1;
- outer: for (ComponentParams subcomponentJson : componentJson.submodel.components)
- {
- Tuple2<List<String>, List<Integer>> subcomponentInterfacePinNamesAndWidths = getSubcomponentInterfacePinNamesAndWidths(
- subcomponentJson.id, subcomponentJson.params);
- List<String> subcomponentInterfacePinNames = subcomponentInterfacePinNamesAndWidths.e1;
- List<Integer> subcomponentInterfacePinWidths = subcomponentInterfacePinNamesAndWidths.e2;
- for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
- if (s.contains(pinIdentifierGenerator.getPinID(subcomponentJson.name, subcomponentInterfacePinNames.get(i))))
- {
- logicWidth = subcomponentInterfacePinWidths.get(i);
- break outer;
- }
- }
- appendLogicWidth(result, logicWidth);
- result.append(sanitizeVerilog(resultWireName));
- result.append(";\n");
-
- result.append("assign ");
- result.append(sanitizeVerilog(resultWireName));
- result.append(" = rst ? ");
- result.append(logicWidth * 2);
- result.append("'b");
- for (int i = 0; i < logicWidth; i++)
- result.append("10");
- result.append(" : ");
- result.append(sanitizeVerilog(lastWireName));
- result.append(";\n");
- }
- }
-
- private void appendComponent(StringBuilder result, Map<Set<String>, String> currentWireNamePerCombinedInnerPinNames,
- Map<Set<String>, String> resultWireNamePerCombinedInnerPinNames, ComponentParams subcomponentParams)
- {
- {
- String subcomponentID = subcomponentParams.id;
- String subcomponentName = subcomponentParams.name;
-
- Tuple2<List<String>, List<Integer>> subcomponentInterfacePinNamesAndWidths = getSubcomponentInterfacePinNamesAndWidths(
- subcomponentID, subcomponentParams.params);
- List<String> subcomponentInterfacePinNames = subcomponentInterfacePinNamesAndWidths.e1;
- List<Integer> subcomponentInterfacePinWidths = subcomponentInterfacePinNamesAndWidths.e2;
- for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
- {
- result.append("wire ");
- appendLogicWidth(result, subcomponentInterfacePinWidths.get(i));
- result.append(pinIdentifierGenerator.getPinID(subcomponentName, subcomponentInterfacePinNames.get(i)));
- result.append(";\n");
- }
-
- result.append(COMPONENT_PREFIX);
- String paramsString = subcomponentParams.params == JsonNull.INSTANCE ? "" : subcomponentParams.params.toString();
- result.append(sanitizeVerilog(subcomponentID + paramsString));
- result.append(' ');
- // abuse the pinIdentifierGenerator for making these unique
- result.append(pinIdentifierGenerator.getPinID("comp", subcomponentName));
- result.append(" (rst, clk");
- for (int i = 0; i < subcomponentInterfacePinNames.size(); i++)
- {
- result.append(",\n ");
- String innerPinID = pinIdentifierGenerator.getPinID(subcomponentName, subcomponentInterfacePinNames.get(i));
-
- String lastWireName;
- String nextWireName = innerPinID;
- String resultWireName;
- Set<String> combinedInnerPinsGroup = combinedInnerPinNames.get(innerPinID);
- if (combinedInnerPinsGroup != null)
- {
- lastWireName = currentWireNamePerCombinedInnerPinNames.get(combinedInnerPinsGroup);
- resultWireName = resultWireNamePerCombinedInnerPinNames.get(combinedInnerPinsGroup);
-
- currentWireNamePerCombinedInnerPinNames.put(combinedInnerPinsGroup, nextWireName);
- } else
- {
- lastWireName = "2'b00";
- resultWireName = nextWireName;
- }
-
- result.append(sanitizeVerilog(lastWireName));
- result.append(", ");
- result.append(sanitizeVerilog(nextWireName));
- result.append(", ");
- result.append(sanitizeVerilog(resultWireName));
- }
- result.append(");\n\n");
- }
- }
-
- private static Map<Tuple2<String, JsonElement>, Tuple2<List<String>, List<Integer>>> atomicComponentInterfaces = new HashMap<>();
-
- private Tuple2<List<String>, List<Integer>> getSubcomponentInterfacePinNamesAndWidths(String subcomponentID,
- JsonElement subcomponentParams)
- {
- Tuple2<List<String>, List<Integer>> result = sortedInterfacePinNamesAndWidthsPerComponentID.get(subcomponentID);
- if (result != null)
- return result;
-
- Tuple2<String, JsonElement> subcomponentKey = new Tuple2<>(subcomponentID, subcomponentParams);
-
- result = atomicComponentInterfaces.get(subcomponentKey);
- if (result != null)
- return result;
-
- Map<String, Pin> pins = IndirectModelComponentCreator
- .createComponent(new LogicModelModifiable(), subcomponentID, subcomponentParams).getPins();
- List<String> names = pins.keySet().stream().sorted().collect(Collectors.toList());
- List<Integer> widthes = pins.entrySet().stream().sorted(Comparator.comparing(e -> e.getKey())).map(Entry::getValue)
- .map(p -> p.logicWidth).collect(Collectors.toList());
- System.out.println(
- "Assuming following order for interface pins of " + subcomponentID + " with params " + subcomponentParams + ": " + names);
- result = new Tuple2<>(names, widthes);
-
- atomicComponentInterfaces.put(subcomponentKey, result);
- return result;
- }
-
- private static void appendLogicWidth(StringBuilder result, int logicWidth)
- {
- result.append('[');
- String logicWidthStr = Integer.toString(logicWidth * 2 - 1);
- for (int spaces = logicWidthStr.length(); spaces < 3; spaces++)
- result.append(' ');
- result.append(logicWidthStr);
- result.append(":0] ");
- }
-
- private static class PinIdentifierGenerator
- {
- private final Map<String, Map<String, String>> wireNamesPerPinAndComponentName;
- private final Set<String> usedWireNames;
-
- public PinIdentifierGenerator()
- {
- wireNamesPerPinAndComponentName = new HashMap<>();
- usedWireNames = new HashSet<>();
- }
-
- private String getPinID(PinParams pin)
- {
- return getPinID(pin.compName, pin.pinName);
- }
-
- private String getPinID(String component, String pin)
- {
- String componentSan = sanitizeVerilog(component);
- String pinSan = sanitizeVerilog(pin);
-
- Map<String, String> wireNamesPerPinName = wireNamesPerPinAndComponentName.computeIfAbsent(componentSan, k -> new HashMap<>());
-
- if (wireNamesPerPinName.containsKey(pinSan))
- return wireNamesPerPinName.get(pinSan);
-
- String baseName = componentSan + '_' + pinSan;
- String combinedName;
- if (usedWireNames.add(baseName))
- combinedName = baseName;
- else
- {
- int i = 0;
- do
- combinedName = baseName + "#" + i++;
- while (!usedWireNames.add(combinedName));
- }
- wireNamesPerPinName.put(pinSan, combinedName);
- return combinedName;
- }
- }
-
- private static class Tuple2<E1, E2>
- {
- public final E1 e1;
- public final E2 e2;
-
- public Tuple2(E1 e1, E2 e2)
- {
- this.e1 = e1;
- this.e2 = e2;
- }
-
- @Override
- public int hashCode()
- {
- final int prime = 31;
- int result = 1;
- result = prime * result + ((e1 == null) ? 0 : e1.hashCode());
- result = prime * result + ((e2 == null) ? 0 : e2.hashCode());
- return result;
- }
-
- @Override
- public boolean equals(Object obj)
- {
- if (this == obj)
- return true;
- if (obj == null)
- return false;
- if (getClass() != obj.getClass())
- return false;
- Tuple2<?, ?> other = (Tuple2<?, ?>) obj;
- if (e1 == null)
- {
- if (other.e1 != null)
- return false;
- } else if (!e1.equals(other.e1))
- return false;
- if (e2 == null)
- {
- if (other.e2 != null)
- return false;
- } else if (!e2.equals(other.e2))
- return false;
- return true;
- }
- }
-
- private static String sanitizeVerilog(String str)
- {
- return str.replace('#', '_').replace('+', '_').replace('-', '_').replace('=', '_').replace('{', '_').replace('}', '_')
- .replace(':', '_').replace('"', '_').replace(',', '_').replace('[', '_').replace(']', '_').replace(' ', '_');
- }
-}
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+ <classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER/org.eclipse.jdt.internal.debug.ui.launcher.StandardVMType/JavaSE-11">
+ <attributes>
+ <attribute name="module" value="true"/>
+ </attributes>
+ </classpathentry>
+ <classpathentry kind="con" path="org.eclipse.pde.core.requiredPlugins"/>
+ <classpathentry kind="src" path="src"/>
+ <classpathentry kind="output" path="bin/src"/>
+</classpath>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>net.mograsim.logic.model.verilog</name>
+ <comment></comment>
+ <projects>
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--- /dev/null
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--- /dev/null
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+ "compName": "Am2904#0",
+ "pinName": "_EN"
+ },
+ "name": "unnamedWire#11",
+ "path": [
+ {
+ "x": 200.0,
+ "y": 240.0
+ },
+ {
+ "x": 200.0,
+ "y": 215.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "I"
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "I"
+ },
+ "name": "unnamedWire#12",
+ "path": [
+ {
+ "x": 105.0,
+ "y": 190.0
+ },
+ {
+ "x": 105.0,
+ "y": 265.0
+ },
+ {
+ "x": 210.0,
+ "y": 265.0
+ },
+ {
+ "x": 210.0,
+ "y": 235.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#14",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "Cx"
+ },
+ "name": "unnamedWire#13",
+ "path": [
+ {
+ "x": 200.0,
+ "y": 295.0
+ },
+ {
+ "x": 200.0,
+ "y": 285.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "YOVR"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#12",
+ "pinName": ""
+ },
+ "name": "unnamedWire#14",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#11",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "YN"
+ },
+ "name": "unnamedWire#15",
+ "path": [
+ {
+ "x": 375.0,
+ "y": 195.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#10",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#1",
+ "pinName": ""
+ },
+ "name": "unnamedWire#16",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "YZ"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#9",
+ "pinName": ""
+ },
+ "name": "unnamedWire#17",
+ "path": [
+ {
+ "x": 365.0,
+ "y": 185.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "CT"
+ },
+ "pin2": {
+ "compName": "BitDisplay#4",
+ "pinName": ""
+ },
+ "name": "unnamedWire#18",
+ "path": [
+ {
+ "x": 345.0,
+ "y": 235.0
+ },
+ {
+ "x": 345.0,
+ "y": 250.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "C0"
+ },
+ "pin2": {
+ "compName": "BitDisplay#5",
+ "pinName": ""
+ },
+ "name": "unnamedWire#19",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "SIOn"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#2",
+ "pinName": ""
+ },
+ "name": "unnamedWire#20",
+ "path": [
+ {
+ "x": 210.0,
+ "y": 295.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#2",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#0",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#21",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#3",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "QIOn"
+ },
+ "name": "unnamedWire#22",
+ "path": [
+ {
+ "x": 215.0,
+ "y": 305.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#1",
+ "pinName": "OUT"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#3",
+ "pinName": ""
+ },
+ "name": "unnamedWire#23",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#15",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#0",
+ "pinName": "IN"
+ },
+ "name": "unnamedWire#24",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#16",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#1",
+ "pinName": "IN"
+ },
+ "name": "unnamedWire#25",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#2",
+ "pinName": "IN"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#17",
+ "pinName": ""
+ },
+ "name": "unnamedWire#26",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#18",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#3",
+ "pinName": "IN"
+ },
+ "name": "unnamedWire#27",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#19",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#0",
+ "pinName": ""
+ },
+ "name": "unnamedWire#28",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#0",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#3",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#29",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#0",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#2",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#30",
+ "path": [
+ {
+ "x": 200.0,
+ "y": 365.0
+ },
+ {
+ "x": 200.0,
+ "y": 390.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#20",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#1",
+ "pinName": ""
+ },
+ "name": "unnamedWire#31",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#1",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#0",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#32",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#1",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#1",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#33",
+ "path": [
+ {
+ "x": 200.0,
+ "y": 310.0
+ },
+ {
+ "x": 200.0,
+ "y": 335.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#2",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#9",
+ "pinName": ""
+ },
+ "name": "unnamedWire#34",
+ "path": [
+ {
+ "x": 210.0,
+ "y": 375.0
+ },
+ {
+ "x": 345.0,
+ "y": 375.0
+ },
+ {
+ "x": 345.0,
+ "y": 325.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "BitDisplay#8",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#3",
+ "pinName": ""
+ },
+ "name": "unnamedWire#35",
+ "path": [
+ {
+ "x": 350.0,
+ "y": 340.0
+ },
+ {
+ "x": 350.0,
+ "y": 380.0
+ },
+ {
+ "x": 215.0,
+ "y": 380.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#3",
+ "pinName": "OUT"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#4",
+ "pinName": ""
+ },
+ "name": "unnamedWire#36",
+ "path": [
+ {
+ "x": 210.0,
+ "y": 380.0
+ },
+ {
+ "x": 210.0,
+ "y": 385.0
+ },
+ {
+ "x": 355.0,
+ "y": 385.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#5",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#2",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#37",
+ "path": [
+ {
+ "x": 210.0,
+ "y": 390.0
+ },
+ {
+ "x": 210.0,
+ "y": 395.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#5",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#7",
+ "pinName": ""
+ },
+ "name": "unnamedWire#38",
+ "path": [
+ {
+ "x": 360.0,
+ "y": 395.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "BitDisplay#6",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#4",
+ "pinName": ""
+ },
+ "name": "unnamedWire#39",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#4",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "SIO0"
+ },
+ "name": "unnamedWire#40",
+ "path": [
+ {
+ "x": 355.0,
+ "y": 295.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "QIO0"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#5",
+ "pinName": ""
+ },
+ "name": "unnamedWire#41",
+ "path": [
+ {
+ "x": 360.0,
+ "y": 305.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#3",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O12"
+ },
+ "name": "unnamedWire#42",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O11"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#13",
+ "pinName": ""
+ },
+ "name": "unnamedWire#43",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#21",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O10"
+ },
+ "name": "unnamedWire#44",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O9"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#22",
+ "pinName": ""
+ },
+ "name": "unnamedWire#45",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#24",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O8"
+ },
+ "name": "unnamedWire#46",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O7"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#23",
+ "pinName": ""
+ },
+ "name": "unnamedWire#47",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#25",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O6"
+ },
+ "name": "unnamedWire#48",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O5"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#26",
+ "pinName": ""
+ },
+ "name": "unnamedWire#49",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#28",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O4"
+ },
+ "name": "unnamedWire#50",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O3"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#30",
+ "pinName": ""
+ },
+ "name": "unnamedWire#51",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#29",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O2"
+ },
+ "name": "unnamedWire#52",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "Splitter#0",
+ "pinName": "O1"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#27",
+ "pinName": ""
+ },
+ "name": "unnamedWire#53",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#31",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Splitter#0",
+ "pinName": "O0"
+ },
+ "name": "unnamedWire#54",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#7",
+ "pinName": "IN"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#33",
+ "pinName": ""
+ },
+ "name": "unnamedWire#55",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#35",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#6",
+ "pinName": "IN"
+ },
+ "name": "unnamedWire#56",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#4",
+ "pinName": "IN"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#32",
+ "pinName": ""
+ },
+ "name": "unnamedWire#57",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#34",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#5",
+ "pinName": "IN"
+ },
+ "name": "unnamedWire#58",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#6",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#5",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#59",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#6",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "ManualSwitch#36",
+ "pinName": ""
+ },
+ "name": "unnamedWire#60",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#6",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#7",
+ "pinName": ""
+ },
+ "name": "unnamedWire#61",
+ "path": [
+ {
+ "x": 360.0,
+ "y": 85.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#7",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#4",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#62",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#7",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#8",
+ "pinName": ""
+ },
+ "name": "unnamedWire#63",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#8",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#6",
+ "pinName": "EN"
+ },
+ "name": "unnamedWire#64",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "TriStateBuffer#7",
+ "pinName": "EN"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#8",
+ "pinName": ""
+ },
+ "name": "unnamedWire#65",
+ "path": [
+ {
+ "x": 360.0,
+ "y": 140.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#9",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#0",
+ "pinName": ""
+ },
+ "name": "unnamedWire#66",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#9",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#5",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#67",
+ "path": [
+ {
+ "x": 365.0,
+ "y": 100.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "YC"
+ },
+ "pin2": {
+ "compName": "WireCrossPoint#10",
+ "pinName": ""
+ },
+ "name": "unnamedWire#68",
+ "path": [
+ {
+ "x": 370.0,
+ "y": 190.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#10",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#4",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#69",
+ "path": [
+ {
+ "x": 370.0,
+ "y": 115.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#11",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#6",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#70",
+ "path": [
+ {
+ "x": 375.0,
+ "y": 130.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#11",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#2",
+ "pinName": ""
+ },
+ "name": "unnamedWire#71",
+ "path": []
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#12",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "BitDisplay#3",
+ "pinName": ""
+ },
+ "name": "unnamedWire#72",
+ "path": [
+ {
+ "x": 380.0,
+ "y": 205.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "WireCrossPoint#12",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "TriStateBuffer#7",
+ "pinName": "OUT"
+ },
+ "name": "unnamedWire#73",
+ "path": [
+ {
+ "x": 380.0,
+ "y": 145.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "Am2904#0",
+ "pinName": "_SE"
+ },
+ "pin2": {
+ "compName": "ManualSwitch#37",
+ "pinName": ""
+ },
+ "name": "unnamedWire#74",
+ "path": [
+ {
+ "x": 215.0,
+ "y": 260.0
+ },
+ {
+ "x": 215.0,
+ "y": 280.0
+ }
+ ]
+ },
+ {
+ "pin1": {
+ "compName": "ManualSwitch#38",
+ "pinName": ""
+ },
+ "pin2": {
+ "compName": "Am2904#0",
+ "pinName": "_OECT"
+ },
+ "name": "unnamedWire#75",
+ "path": [
+ {
+ "x": 410.0,
+ "y": 230.0
+ },
+ {
+ "x": 410.0,
+ "y": 215.0
+ },
+ {
+ "x": 345.0,
+ "y": 215.0
+ },
+ {
+ "x": 345.0,
+ "y": 225.0
+ }
+ ]
+ }
+ ],
+ "version": "0.1.1"
+ },
+ "symbolRendererSnippetID": "default",
+ "outlineRendererSnippetID": "default",
+ "highLevelStateHandlerSnippetID": "default",
+ "version": "0.1.5"
+}
\ No newline at end of file
--- /dev/null
+Manifest-Version: 1.0
+Bundle-ManifestVersion: 2
+Bundle-Name: %Bundle-Name
+Bundle-SymbolicName: net.mograsim.logic.model.verilog;singleton:=true
+Bundle-Version: 0.1.4.qualifier
+Bundle-RequiredExecutionEnvironment: JavaSE-11
+Require-Bundle: org.eclipse.osgi,
+ net.mograsim.logic.model;bundle-version="0.1.4";visibility:=reexport
+Automatic-Module-Name: net.mograsim.logic.model.verilogexporter
+Bundle-Vendor: Mograsim Team
+Bundle-ActivationPolicy: lazy
--- /dev/null
+#Properties file for net.mograsim.logic.model.verilog
+Bundle-Vendor = Mograsim Team
+Bundle-Name = Mograsim Verilog
\ No newline at end of file
--- /dev/null
+source.. = src/
+bin.includes = META-INF/,\
+ .,\
+ OSGI-INF/,\
+ plugin.xml
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse version="3.4"?>
+<plugin>
+
+</plugin>
--- /dev/null
+package net.mograsim.logic.model.verilog.converter;
+
+import java.util.ArrayList;
+import java.util.List;
+import java.util.Map;
+import java.util.Objects;
+import java.util.Set;
+import java.util.function.Function;
+import java.util.stream.Collectors;
+
+import com.google.gson.JsonElement;
+
+import net.mograsim.logic.model.verilog.converter.VerilogEmulatedModelPin.Type;
+import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration;
+
+public class ModelComponentToVerilogComponentDeclarationMapping
+{
+ private final String modelComponentID;
+ private final JsonElement modelComponentParams;
+ private final VerilogComponentDeclaration verilogComponentDeclaration;
+ private final Set<VerilogEmulatedModelPin> pinMapping;
+
+ private final Map<PinNameBit, VerilogEmulatedModelPin> prePinMapping;
+ private final Map<PinNameBit, VerilogEmulatedModelPin> outPinMapping;
+ private final Map<PinNameBit, VerilogEmulatedModelPin> resPinMapping;
+ private final List<VerilogEmulatedModelPin> reversePinMapping;
+
+ public ModelComponentToVerilogComponentDeclarationMapping(String modelComponentID, JsonElement modelComponentParams,
+ VerilogComponentDeclaration verilogComponentDeclaration, Set<VerilogEmulatedModelPin> pinMapping)
+ {
+ this.modelComponentID = Objects.requireNonNull(modelComponentID);
+ this.modelComponentParams = Objects.requireNonNull(modelComponentParams);
+ this.verilogComponentDeclaration = Objects.requireNonNull(verilogComponentDeclaration);
+ this.pinMapping = Set.copyOf(pinMapping);
+
+ this.reversePinMapping = checkAndCalculateReversePinMapping();
+
+ this.prePinMapping = filterPinMapping(Type.PRE);
+ this.outPinMapping = filterPinMapping(Type.OUT);
+ this.resPinMapping = filterPinMapping(Type.RES);
+ }
+
+ private List<VerilogEmulatedModelPin> checkAndCalculateReversePinMapping()
+ {
+ List<VerilogEmulatedModelPin> reverseMapping = new ArrayList<>(pinMapping.size());
+ for (int i = 0; i < pinMapping.size(); i++)
+ reverseMapping.add(null);
+ for (VerilogEmulatedModelPin verilogEmulatedModelPin : pinMapping)
+ {
+ int verilogPinIndex = verilogEmulatedModelPin.getPortIndex();
+ if (verilogComponentDeclaration.getIOPorts().get(verilogPinIndex) != verilogEmulatedModelPin.getVerilogPort())
+ throw new IllegalArgumentException("Incorrect IO port index for port: " + verilogEmulatedModelPin);
+ VerilogEmulatedModelPin oldVerilogEmulatedModelPin = reverseMapping.set(verilogPinIndex, verilogEmulatedModelPin);
+ if (oldVerilogEmulatedModelPin != null)
+ throw new IllegalArgumentException("Port is used twice: " + verilogEmulatedModelPin.getVerilogPort());
+ }
+ for (int i = 0; i < reverseMapping.size(); i++)
+ if (reverseMapping.get(i) == null)
+ throw new IllegalArgumentException("Unused IO port: " + verilogComponentDeclaration.getIOPorts().get(i));
+ return reverseMapping;
+ }
+
+ private Map<PinNameBit, VerilogEmulatedModelPin> filterPinMapping(Type filteredType)
+ {
+ return pinMapping.stream().filter(p -> p.getType() == filteredType)
+ .collect(Collectors.toMap(VerilogEmulatedModelPin::getPinbit, Function.identity()));
+ }
+
+ public String getModelComponentID()
+ {
+ return modelComponentID;
+ }
+
+ public JsonElement getModelComponentParams()
+ {
+ return modelComponentParams;
+ }
+
+ public VerilogComponentDeclaration getVerilogComponentDeclaration()
+ {
+ return verilogComponentDeclaration;
+ }
+
+ public Set<VerilogEmulatedModelPin> getPinMapping()
+ {
+ return pinMapping;
+ }
+
+ public Map<PinNameBit, VerilogEmulatedModelPin> getPrePinMapping()
+ {
+ return prePinMapping;
+ }
+
+ public Map<PinNameBit, VerilogEmulatedModelPin> getOutPinMapping()
+ {
+ return outPinMapping;
+ }
+
+ public Map<PinNameBit, VerilogEmulatedModelPin> getResPinMapping()
+ {
+ return resPinMapping;
+ }
+
+ public List<VerilogEmulatedModelPin> getReversePinMapping()
+ {
+ return reversePinMapping;
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((modelComponentID == null) ? 0 : modelComponentID.hashCode());
+ result = prime * result + ((pinMapping == null) ? 0 : pinMapping.hashCode());
+ result = prime * result + ((verilogComponentDeclaration == null) ? 0 : verilogComponentDeclaration.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ ModelComponentToVerilogComponentDeclarationMapping other = (ModelComponentToVerilogComponentDeclarationMapping) obj;
+ if (modelComponentID == null)
+ {
+ if (other.modelComponentID != null)
+ return false;
+ } else if (!modelComponentID.equals(other.modelComponentID))
+ return false;
+ if (pinMapping == null)
+ {
+ if (other.pinMapping != null)
+ return false;
+ } else if (!pinMapping.equals(other.pinMapping))
+ return false;
+ if (verilogComponentDeclaration == null)
+ {
+ if (other.verilogComponentDeclaration != null)
+ return false;
+ } else if (!verilogComponentDeclaration.equals(other.verilogComponentDeclaration))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.converter;
+
+import java.util.ArrayList;
+import java.util.Collection;
+import java.util.HashMap;
+import java.util.HashSet;
+import java.util.List;
+import java.util.Map;
+import java.util.Map.Entry;
+import java.util.Set;
+import java.util.function.BiFunction;
+import java.util.function.Function;
+import java.util.stream.Collectors;
+
+import com.google.gson.JsonElement;
+
+import net.mograsim.logic.core.types.Bit;
+import net.mograsim.logic.core.types.BitVector;
+import net.mograsim.logic.model.model.components.ModelComponent;
+import net.mograsim.logic.model.model.components.atomic.ModelSplitter;
+import net.mograsim.logic.model.model.components.submodels.SubmodelComponent;
+import net.mograsim.logic.model.model.wires.ModelWire;
+import net.mograsim.logic.model.model.wires.Pin;
+import net.mograsim.logic.model.serializing.IdentifyParams;
+import net.mograsim.logic.model.verilog.converter.VerilogEmulatedModelPin.Type;
+import net.mograsim.logic.model.verilog.helper.IdentifierGenerator;
+import net.mograsim.logic.model.verilog.helper.UnionFind;
+import net.mograsim.logic.model.verilog.helper.UnionFind.UnionFindElement;
+import net.mograsim.logic.model.verilog.model.Assign;
+import net.mograsim.logic.model.verilog.model.ComponentReference;
+import net.mograsim.logic.model.verilog.model.Constant;
+import net.mograsim.logic.model.verilog.model.IOPort;
+import net.mograsim.logic.model.verilog.model.Input;
+import net.mograsim.logic.model.verilog.model.NamedSignal;
+import net.mograsim.logic.model.verilog.model.Output;
+import net.mograsim.logic.model.verilog.model.Signal;
+import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration;
+import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation;
+import net.mograsim.logic.model.verilog.model.Wire;
+
+public class ModelComponentToVerilogConverter
+{
+ private final String verilogComponentIDPrefix;
+ private final Map<String, Map<JsonElement, ModelComponentToVerilogComponentDeclarationMapping>> componentMappingsPerModelIDPerParams;
+ private final Set<VerilogComponentImplementation> verilogComponents;
+ private final IdentifierGenerator verilogComponentIDGen;
+
+ public ModelComponentToVerilogConverter(String verilogComponentIDPrefix,
+ Set<ModelComponentToVerilogComponentDeclarationMapping> atomicComponentMappings)
+ {
+ this.verilogComponentIDPrefix = verilogComponentIDPrefix;
+ this.componentMappingsPerModelIDPerParams = new HashMap<>(atomicComponentMappings.stream().collect(Collectors
+ .groupingBy(m -> m.getModelComponentID(), Collectors.toMap(m -> m.getModelComponentParams(), Function.identity()))));
+ this.verilogComponents = new HashSet<>();
+ this.verilogComponentIDGen = new IdentifierGenerator(
+ componentMappingsPerModelIDPerParams.values().stream().map(Map::values).flatMap(Collection::stream)
+ .map(ModelComponentToVerilogComponentDeclarationMapping::getVerilogComponentDeclaration)
+ .map(VerilogComponentDeclaration::getID).collect(Collectors.toSet()),
+ ModelComponentToVerilogConverter::sanitizeVerilogID);
+ }
+
+ private void convert(ModelComponent modelComponent)
+ {
+ String modelID = modelComponent.getIDForSerializing(new IdentifyParams());
+ JsonElement params = modelComponent.getParamsForSerializingJSON(new IdentifyParams());
+ if (componentMappingsPerModelIDPerParams.getOrDefault(modelID, Map.of()).containsKey(params))
+ // we already converted that component, or it was specified externally
+ return;
+
+ if (!(modelComponent instanceof SubmodelComponent))
+ throw new IllegalArgumentException(
+ "Can only convert SubmodelComponents, tried to convert " + modelID + " with params " + params);
+ SubmodelComponent modelComponentC = (SubmodelComponent) modelComponent;
+
+ ModelComponentToVerilogComponentDeclarationMapping mapping = mapDeclaration(modelComponentC, modelID, params);
+ componentMappingsPerModelIDPerParams.computeIfAbsent(modelID, i -> new HashMap<>()).put(params, mapping);
+
+ for (ModelComponent subcomponent : modelComponentC.submodel.getComponentsByName().values())
+ if (!subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME))
+ convert(subcomponent);
+
+ verilogComponents.add(mapImplementation(modelComponentC, mapping));
+ }
+
+ private ModelComponentToVerilogComponentDeclarationMapping mapDeclaration(ModelComponent modelComponent, String modelID,
+ JsonElement params)
+ {
+ return generateCanonicalDeclarationMapping(modelComponent, modelID, params,
+ verilogComponentIDGen.generateID(verilogComponentIDPrefix + modelID + (params.isJsonNull() ? "" : "_" + params)));
+ }
+
+ public static ModelComponentToVerilogComponentDeclarationMapping generateCanonicalDeclarationMapping(ModelComponent modelComponent,
+ String modelID, JsonElement params, String verilogID)
+ {
+ IdentifierGenerator ioPortIDGen = new IdentifierGenerator(ModelComponentToVerilogConverter::sanitizeVerilogID);
+ List<IOPort> ioPorts = new ArrayList<>();
+ Set<VerilogEmulatedModelPin> pinMapping = new HashSet<>();
+ for (Pin modelPin : modelComponent.getPins().values())
+ for (int bit = 0; bit < modelPin.logicWidth; bit++)
+ {
+ addPinMapping(ioPortIDGen, ioPorts, pinMapping, modelPin, bit, Input::new, Type.PRE, "pre");
+ addPinMapping(ioPortIDGen, ioPorts, pinMapping, modelPin, bit, Output::new, Type.OUT, "out");
+ addPinMapping(ioPortIDGen, ioPorts, pinMapping, modelPin, bit, Input::new, Type.RES, "res");
+ }
+
+ VerilogComponentDeclaration declaration = new VerilogComponentDeclaration(verilogID, ioPorts);
+ return new ModelComponentToVerilogComponentDeclarationMapping(modelID, params, declaration, pinMapping);
+ }
+
+ private static void addPinMapping(IdentifierGenerator ioPortIDGen, List<IOPort> ioPorts, Set<VerilogEmulatedModelPin> pinMapping,
+ Pin modelPin, int bit, BiFunction<String, Integer, IOPort> constr, Type type, String suffix)
+ {
+ String portID = ioPortIDGen.generateID(modelPin.name + "_" + bit + "_" + suffix);
+ IOPort ioPort = constr.apply(portID, 2);
+ int index = ioPorts.size();
+ ioPorts.add(ioPort);
+ pinMapping.add(new VerilogEmulatedModelPin(ioPort, index, new PinNameBit(modelPin.name, bit), type));
+ }
+
+ private VerilogComponentImplementation mapImplementation(SubmodelComponent modelComponent,
+ ModelComponentToVerilogComponentDeclarationMapping declarationMapping)
+ {
+ UnionFind<PinBit> connectedPins = new UnionFind<>();
+ for (ModelWire w : modelComponent.submodel.getWiresByName().values())
+ for (int bit = 0; bit < w.getPin1().logicWidth; bit++)
+ connectedPins.union(new PinBit(w.getPin1(), bit), new PinBit(w.getPin2(), bit));
+
+ Map<UnionFindElement<PinBit>, Signal> currentPreSignals = new HashMap<>();
+ Map<UnionFindElement<PinBit>, NamedSignal> finalOutSignals = new HashMap<>();
+ Map<UnionFindElement<PinBit>, NamedSignal> resSignals = new HashMap<>();
+ for (Pin submodelPin : modelComponent.getSubmodelPins().values())
+ for (int bit = 0; bit < submodelPin.logicWidth; bit++)
+ {
+ PinBit pinbit = new PinBit(submodelPin, bit);
+ PinNameBit pinnamebit = pinbit.toPinNameBit();
+ UnionFindElement<PinBit> root = UnionFind.find(connectedPins.getElement(pinbit));
+ resSignals.put(root, declarationMapping.getResPinMapping().get(pinnamebit).getVerilogPort());
+ finalOutSignals.put(root, declarationMapping.getOutPinMapping().get(pinnamebit).getVerilogPort());
+ Signal prePort = declarationMapping.getPrePinMapping().get(pinnamebit).getVerilogPort();
+ Signal previousPrePort = currentPreSignals.put(root, prePort);
+ if (previousPrePort != null)
+ // TODO implement this
+ throw new IllegalArgumentException("Can't convert components with connected pins");
+ }
+
+ IdentifierGenerator idGen = new IdentifierGenerator(
+ declarationMapping.getVerilogComponentDeclaration().getIOPorts().stream().map(IOPort::getName).collect(Collectors.toList()),
+ ModelComponentToVerilogConverter::sanitizeVerilogID);
+ Set<Wire> internalWires = new HashSet<>();
+ Set<ComponentReference> subcomponents = new HashSet<>();
+ for (ModelComponent subcomponent : modelComponent.submodel.getComponentsByName().values())
+ {
+ // TODO do we really want to use instanceof?
+ if (subcomponent instanceof ModelSplitter || subcomponent.getName().equals(SubmodelComponent.SUBMODEL_INTERFACE_NAME))
+ continue;
+
+ String subcomponentVerilogName = idGen.generateID(subcomponent.getName());
+ ModelComponentToVerilogComponentDeclarationMapping subcomponentMapping = componentMappingsPerModelIDPerParams
+ .get(subcomponent.getIDForSerializing(new IdentifyParams()))
+ .get(subcomponent.getParamsForSerializingJSON(new IdentifyParams()));
+ int parameterCount = subcomponentMapping.getVerilogComponentDeclaration().getIOPorts().size();
+ List<Signal> arguments = new ArrayList<>(parameterCount);
+ for (int i = 0; i < parameterCount; i++)
+ arguments.add(null);
+ for (Pin pin : subcomponent.getPins().values())
+ for (int bit = 0; bit < pin.logicWidth; bit++)
+ {
+ PinBit pinbit = new PinBit(pin, bit);
+ UnionFindElement<PinBit> root = UnionFind.find(connectedPins.getElement(pinbit));
+ Wire outSignal = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit), 2);
+ internalWires.add(outSignal);
+ Signal preSignal = currentPreSignals.put(root, outSignal);
+ Signal resSignal = resSignals.get(root);
+ if (resSignal == null)
+ {
+ preSignal = new Constant(BitVector.of(Bit.ZERO, 2));
+ Wire resWire = new Wire(idGen.generateID(subcomponentVerilogName + "_" + pin.name + "_" + bit + "_res"), 2);
+ resSignal = resWire;
+ internalWires.add(resWire);
+ finalOutSignals.put(root, resWire);
+ resSignals.put(root, resWire);
+ }
+ PinNameBit pinnamebit = pinbit.toPinNameBit();
+ arguments.set(subcomponentMapping.getPrePinMapping().get(pinnamebit).getPortIndex(), preSignal);
+ arguments.set(subcomponentMapping.getOutPinMapping().get(pinnamebit).getPortIndex(), outSignal);
+ arguments.set(subcomponentMapping.getResPinMapping().get(pinnamebit).getPortIndex(), resSignal);
+ }
+ subcomponents
+ .add(new ComponentReference(subcomponentVerilogName, subcomponentMapping.getVerilogComponentDeclaration(), arguments));
+ }
+
+ Set<Assign> assigns = new HashSet<>();
+ for (Entry<UnionFindElement<PinBit>, NamedSignal> e : finalOutSignals.entrySet())
+ assigns.add(new Assign(currentPreSignals.get(e.getKey()), e.getValue()));
+
+ return new VerilogComponentImplementation(declarationMapping.getVerilogComponentDeclaration(), internalWires, assigns,
+ subcomponents);
+ }
+
+ private Set<VerilogComponentImplementation> getVerilogComponents()
+ {
+ return verilogComponents;
+ }
+
+ public static Set<VerilogComponentImplementation> convert(
+ Set<ModelComponentToVerilogComponentDeclarationMapping> atomicComponentMappings, Set<ModelComponent> components,
+ String verilogComponentIDPrefix)
+ {
+ ModelComponentToVerilogConverter converter = new ModelComponentToVerilogConverter(verilogComponentIDPrefix,
+ atomicComponentMappings);
+ for (ModelComponent modelComponent : components)
+ converter.convert(modelComponent);
+ return converter.getVerilogComponents();
+ }
+
+ public static String sanitizeVerilogID(String id)
+ {
+ return (id.matches("[0-9].*") ? "_" + id : id).replaceAll("[^A-Za-z0-9_]", "_");
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.converter;
+
+import java.util.Objects;
+
+import net.mograsim.logic.model.model.wires.Pin;
+
+public class PinBit
+{
+ private final Pin pin;
+ private final int bit;
+
+ public PinBit(Pin pin, int bit)
+ {
+ this.pin = Objects.requireNonNull(pin);
+ this.bit = bit;
+
+ check();
+ }
+
+ private void check()
+ {
+ if (bit < 0 || bit >= pin.logicWidth)
+ throw new IllegalArgumentException("Bit out of range for pin " + pin + ": " + bit);
+ }
+
+ public Pin getPin()
+ {
+ return pin;
+ }
+
+ public int getBit()
+ {
+ return bit;
+ }
+
+ public PinNameBit toPinNameBit()
+ {
+ return new PinNameBit(pin.name, bit);
+ }
+
+ @Override
+ public String toString()
+ {
+ return pin + "[" + bit + "]";
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + bit;
+ result = prime * result + ((pin == null) ? 0 : pin.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ PinBit other = (PinBit) obj;
+ if (bit != other.bit)
+ return false;
+ if (pin == null)
+ {
+ if (other.pin != null)
+ return false;
+ } else if (!pin.equals(other.pin))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.converter;
+
+import java.util.Objects;
+
+public class PinNameBit
+{
+ private final String name;
+ private final int bit;
+
+ public PinNameBit(String name, int bit)
+ {
+ this.name = Objects.requireNonNull(name);
+ this.bit = bit;
+
+ check();
+ }
+
+ private void check()
+ {
+ if (bit < 0)
+ throw new IllegalArgumentException("Bit out of range: " + bit);
+ }
+
+ public String getName()
+ {
+ return name;
+ }
+
+ public int getBit()
+ {
+ return bit;
+ }
+
+ @Override
+ public String toString()
+ {
+ return name + "[" + bit + "]";
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + bit;
+ result = prime * result + ((name == null) ? 0 : name.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ PinNameBit other = (PinNameBit) obj;
+ if (bit != other.bit)
+ return false;
+ if (name == null)
+ {
+ if (other.name != null)
+ return false;
+ } else if (!name.equals(other.name))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.converter;
+
+import java.util.Objects;
+
+import net.mograsim.logic.model.verilog.model.IOPort;
+import net.mograsim.logic.model.verilog.model.Signal;
+
+public class VerilogEmulatedModelPin
+{
+ private final IOPort verilogPort;
+ private final int portIndex;
+ private final PinNameBit pinbit;
+ private final Type type;
+
+ public VerilogEmulatedModelPin(IOPort verilogPort, int portIndex, PinNameBit pinbit, Type type)
+ {
+ this.verilogPort = Objects.requireNonNull(verilogPort);
+ this.portIndex = portIndex;
+ this.pinbit = Objects.requireNonNull(pinbit);
+ this.type = Objects.requireNonNull(type);
+
+ check();
+ }
+
+ private void check()
+ {
+ if (verilogPort.getWidth() != 2)
+ throw new IllegalArgumentException("Every Verilog port has to have width 2");
+ if (portIndex < 0)
+ throw new IllegalArgumentException("Negative port index can't be negative");
+ switch (type)
+ {
+ case PRE:
+ if (verilogPort.getType() != Signal.Type.IO_INPUT)
+ throw new IllegalArgumentException("A PRE pin has to be an input");
+ break;
+ case OUT:
+ if (verilogPort.getType() != Signal.Type.IO_OUTPUT)
+ throw new IllegalArgumentException("A OUT pin has to be an output");
+ break;
+ case RES:
+ if (verilogPort.getType() != Signal.Type.IO_INPUT)
+ throw new IllegalArgumentException("A RES pin has to be an input");
+ break;
+ default:
+ throw new IllegalStateException("Unknown enum constant: " + type);
+ }
+ }
+
+ public IOPort getVerilogPort()
+ {
+ return verilogPort;
+ }
+
+ public int getPortIndex()
+ {
+ return portIndex;
+ }
+
+ public PinNameBit getPinbit()
+ {
+ return pinbit;
+ }
+
+ public Type getType()
+ {
+ return type;
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((pinbit == null) ? 0 : pinbit.hashCode());
+ result = prime * result + portIndex;
+ result = prime * result + ((type == null) ? 0 : type.hashCode());
+ result = prime * result + ((verilogPort == null) ? 0 : verilogPort.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ VerilogEmulatedModelPin other = (VerilogEmulatedModelPin) obj;
+ if (pinbit == null)
+ {
+ if (other.pinbit != null)
+ return false;
+ } else if (!pinbit.equals(other.pinbit))
+ return false;
+ if (portIndex != other.portIndex)
+ return false;
+ if (type != other.type)
+ return false;
+ if (verilogPort == null)
+ {
+ if (other.verilogPort != null)
+ return false;
+ } else if (!verilogPort.equals(other.verilogPort))
+ return false;
+ return true;
+ }
+
+ public static enum Type
+ {
+ PRE, OUT, RES;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.helper;
+
+import java.util.Collection;
+import java.util.HashSet;
+import java.util.Set;
+import java.util.function.Function;
+
+public class IdentifierGenerator
+{
+ private final Function<String, String> sanitizer;
+ private final Set<String> usedIdentifiers;
+
+ public IdentifierGenerator()
+ {
+ this(Function.identity());
+ }
+
+ public IdentifierGenerator(Function<String, String> sanitizer)
+ {
+ this.usedIdentifiers = new HashSet<>();
+ this.sanitizer = sanitizer;
+ }
+
+ public IdentifierGenerator(Collection<String> forbiddenIDs)
+ {
+ this(forbiddenIDs, Function.identity());
+ }
+
+ public IdentifierGenerator(Collection<String> forbiddenIDs, Function<String, String> sanitizer)
+ {
+ this.usedIdentifiers = new HashSet<>(forbiddenIDs);
+ this.sanitizer = sanitizer;
+ }
+
+ public String generateID(String hint)
+ {
+ String sanitized = sanitizer.apply(hint);
+ if (usedIdentifiers.add(sanitized))
+ return sanitized;
+
+ String idBase = sanitized.isEmpty() ? "_" : sanitized;
+ for (int i = 0;; i++)
+ if (usedIdentifiers.add(idBase + i))
+ return idBase + i;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.helper;
+
+import java.util.HashMap;
+import java.util.Map;
+
+public class UnionFind<E>
+{
+ private final Map<E, UnionFindElement<E>> elements;
+
+ public UnionFind()
+ {
+ this.elements = new HashMap<>();
+ }
+
+ public UnionFindElement<E> getElement(E e)
+ {
+ return elements.computeIfAbsent(e, UnionFindElement::new);
+ }
+
+ public E find(E e)
+ {
+ return find(getElement(e)).getE();
+ }
+
+ public static <E> UnionFindElement<E> find(UnionFindElement<E> elem)
+ {
+ if (elem == elem.parent)
+ return elem;
+ return elem.parent = find(elem.parent);
+ }
+
+ public E union(E e1, E e2)
+ {
+ return union(getElement(e1), getElement(e2)).getE();
+ }
+
+ public static <E> UnionFindElement<E> union(UnionFindElement<E> e1, UnionFindElement<E> e2)
+ {
+ UnionFindElement<E> e1Root = find(e1);
+ UnionFindElement<E> e2Root = find(e2);
+
+ if (e1Root == e2Root)
+ return e1Root;
+
+ if (e1Root.rank < e2Root.rank)
+ return e1Root.parent = e2Root;
+ else if (e1Root.rank > e2Root.rank)
+ return e2Root.parent = e1Root;
+ else
+ {
+ e2Root.rank++;
+ return e1Root.parent = e2Root;
+ }
+ }
+
+ public static class UnionFindElement<E>
+ {
+ private final E e;
+ private UnionFindElement<E> parent;
+ private int rank;
+
+ private UnionFindElement(E e)
+ {
+ this.e = e;
+ this.parent = this;
+ }
+
+ public E getE()
+ {
+ return e;
+ }
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.Objects;
+
+public class Assign
+{
+ private final Signal source;
+ private final NamedSignal target;
+
+ public Assign(Signal source, NamedSignal target)
+ {
+ this.source = Objects.requireNonNull(source);
+ this.target = Objects.requireNonNull(target);
+
+ check();
+ }
+
+ private void check()
+ {
+ if (source.getWidth() != target.getWidth())
+ throw new IllegalArgumentException("Signal widthes don't match");
+ }
+
+ public Signal getSource()
+ {
+ return source;
+ }
+
+ public Signal getTarget()
+ {
+ return target;
+ }
+
+ public String toVerilogCode()
+ {
+ return "assign " + target.toReferenceVerilogCode() + " = " + source.toReferenceVerilogCode() + ";";
+ }
+
+ @Override
+ public String toString()
+ {
+ return target.getName() + " = " + source.toReferenceVerilogCode();
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((source == null) ? 0 : source.hashCode());
+ result = prime * result + ((target == null) ? 0 : target.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ Assign other = (Assign) obj;
+ if (source == null)
+ {
+ if (other.source != null)
+ return false;
+ } else if (!source.equals(other.source))
+ return false;
+ if (target == null)
+ {
+ if (other.target != null)
+ return false;
+ } else if (!target.equals(other.target))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.List;
+import java.util.Objects;
+import java.util.stream.Collectors;
+
+public class ComponentReference
+{
+ private final String name;
+ private final VerilogComponentDeclaration referencedComponent;
+ private final List<Signal> arguments;
+
+ public ComponentReference(String name, VerilogComponentDeclaration referencedComponent, List<Signal> arguments)
+ {
+ this.name = Objects.requireNonNull(name);
+ this.referencedComponent = Objects.requireNonNull(referencedComponent);
+ this.arguments = List.copyOf(arguments);
+
+ check();
+ }
+
+ private void check()
+ {
+ List<IOPort> ioPorts = referencedComponent.getIOPorts();
+ if (ioPorts.size() != arguments.size())
+ throw new IllegalArgumentException(
+ "Incorrect nubmer of arguments given: " + arguments.size() + ", but should be " + ioPorts.size());
+
+ for (int i = 0; i < ioPorts.size(); i++)
+ if (ioPorts.get(i).getWidth() != arguments.get(i).getWidth())
+ throw new IllegalArgumentException("Argument #" + i + "(" + ioPorts.get(i) + "): Incorrect width: "
+ + arguments.get(i).getWidth() + ", but shoud be " + ioPorts.get(i).getWidth());
+ }
+
+ public String getName()
+ {
+ return name;
+ }
+
+ public VerilogComponentDeclaration getReferencedComponent()
+ {
+ return referencedComponent;
+ }
+
+ public List<Signal> getArguments()
+ {
+ return arguments;
+ }
+
+ public String toVerilogCode()
+ {
+ StringBuilder sb = new StringBuilder();
+
+ sb.append(referencedComponent.getID() + " " + name);
+ sb.append(arguments.stream().map(Signal::toReferenceVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+ sb.append(";");
+
+ return sb.toString();
+ }
+
+ @Override
+ public String toString()
+ {
+ return name + "[" + referencedComponent.getID() + "]";
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((arguments == null) ? 0 : arguments.hashCode());
+ result = prime * result + ((name == null) ? 0 : name.hashCode());
+ result = prime * result + ((referencedComponent == null) ? 0 : referencedComponent.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ ComponentReference other = (ComponentReference) obj;
+ if (arguments == null)
+ {
+ if (other.arguments != null)
+ return false;
+ } else if (!arguments.equals(other.arguments))
+ return false;
+ if (name == null)
+ {
+ if (other.name != null)
+ return false;
+ } else if (!name.equals(other.name))
+ return false;
+ if (referencedComponent == null)
+ {
+ if (other.referencedComponent != null)
+ return false;
+ } else if (!referencedComponent.equals(other.referencedComponent))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import net.mograsim.logic.core.types.BitVector;
+
+public class Constant extends Signal
+{
+ private final BitVector constant;
+
+ public Constant(BitVector constant)
+ {
+ super(Type.CONSTANT, constant.length());
+ this.constant = constant;
+
+ check();
+ }
+
+ private void check()
+ {
+ if (!constant.isBinary())
+ throw new IllegalArgumentException("Constant is not binary: " + constant);
+ }
+
+ public BitVector getConstant()
+ {
+ return constant;
+ }
+
+ @Override
+ public String toReferenceVerilogCode()
+ {
+ return getWidth() + "'b" + constant.toBitstring();
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = super.hashCode();
+ result = prime * result + ((constant == null) ? 0 : constant.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (!super.equals(obj))
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ Constant other = (Constant) obj;
+ if (constant == null)
+ {
+ if (other.constant != null)
+ return false;
+ } else if (!constant.equals(other.constant))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+public abstract class IOPort extends NamedSignal
+{
+ public IOPort(Type type, String name, int width)
+ {
+ super(type, name, width);
+ }
+
+ public abstract String toDeclarationVerilogCode();
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+public class Input extends IOPort
+{
+ public Input(String name, int width)
+ {
+ super(Type.IO_INPUT, name, width);
+ }
+
+ @Override
+ public String toDeclarationVerilogCode()
+ {
+ return "input [" + getWidth() + ":0] " + getName();
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.Objects;
+
+public abstract class NamedSignal extends Signal
+{
+ private final String name;
+
+ public NamedSignal(Type type, String name, int width)
+ {
+ super(type, width);
+ this.name = Objects.requireNonNull(name);
+ }
+
+ public String getName()
+ {
+ return name;
+ }
+
+ @Override
+ public String toReferenceVerilogCode()
+ {
+ return name;
+ }
+
+ @Override
+ public String toString()
+ {
+ return name + "[" + getWidth() + "]";
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = super.hashCode();
+ result = prime * result + ((name == null) ? 0 : name.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (!super.equals(obj))
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ NamedSignal other = (NamedSignal) obj;
+ if (name == null)
+ {
+ if (other.name != null)
+ return false;
+ } else if (!name.equals(other.name))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+public class Output extends IOPort
+{
+ public Output(String name, int width)
+ {
+ super(Type.IO_OUTPUT, name, width);
+ }
+
+ @Override
+ public String toDeclarationVerilogCode()
+ {
+ return "output [" + getWidth() + ":0] " + getName();
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.Objects;
+
+public abstract class Signal
+{
+ private final Type type;
+ private final int width;
+
+ public Signal(Type type, int width)
+ {
+ this.type = Objects.requireNonNull(type);
+ this.width = width;
+
+ check();
+ }
+
+ private void check()
+ {
+ if (width <= 0)
+ throw new IllegalArgumentException("Signal width is negative: " + width);
+ }
+
+ public Type getType()
+ {
+ return type;
+ }
+
+ public int getWidth()
+ {
+ return width;
+ }
+
+ public abstract String toReferenceVerilogCode();
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((type == null) ? 0 : type.hashCode());
+ result = prime * result + width;
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ Signal other = (Signal) obj;
+ if (type != other.type)
+ return false;
+ if (width != other.width)
+ return false;
+ return true;
+ }
+
+ public static enum Type
+ {
+ WIRE, IO_INPUT, IO_OUTPUT, CONSTANT;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.HashSet;
+import java.util.List;
+import java.util.Objects;
+import java.util.Set;
+
+public class VerilogComponentDeclaration
+{
+ private final String id;
+ private final List<IOPort> ioPorts;
+
+ public VerilogComponentDeclaration(String id, List<IOPort> ioPorts)
+ {
+ this.id = Objects.requireNonNull(id);
+ this.ioPorts = List.copyOf(ioPorts);
+
+ check();
+ }
+
+ private void check()
+ {
+ Set<String> usedNames = new HashSet<>();
+
+ for (IOPort ioPort : ioPorts)
+ if (!usedNames.add(ioPort.getName()))
+ throw new IllegalArgumentException("Name occurs twice: " + ioPort.getName());
+ }
+
+ public String getID()
+ {
+ return id;
+ }
+
+ public List<IOPort> getIOPorts()
+ {
+ return ioPorts;
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((ioPorts == null) ? 0 : ioPorts.hashCode());
+ result = prime * result + ((id == null) ? 0 : id.hashCode());
+ return result;
+ }
+
+ @Override
+ public String toString()
+ {
+ return id + "[" + ioPorts.size() + "]";
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ VerilogComponentDeclaration other = (VerilogComponentDeclaration) obj;
+ if (ioPorts == null)
+ {
+ if (other.ioPorts != null)
+ return false;
+ } else if (!ioPorts.equals(other.ioPorts))
+ return false;
+ if (id == null)
+ {
+ if (other.id != null)
+ return false;
+ } else if (!id.equals(other.id))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+import java.util.ArrayList;
+import java.util.HashSet;
+import java.util.List;
+import java.util.Objects;
+import java.util.Set;
+import java.util.stream.Collectors;
+
+import net.mograsim.logic.model.verilog.model.Signal.Type;
+
+public class VerilogComponentImplementation
+{
+ private final VerilogComponentDeclaration declaration;
+ private final Set<Wire> internalWires;
+ private final Set<Assign> assigns;
+ private final Set<ComponentReference> subcomponents;
+
+ public VerilogComponentImplementation(VerilogComponentDeclaration declaration, Set<Wire> internalWires, Set<Assign> assigns,
+ Set<ComponentReference> subcomponents)
+ {
+ this.declaration = Objects.requireNonNull(declaration);
+ this.internalWires = Set.copyOf(internalWires);
+ this.assigns = Set.copyOf(assigns);
+ this.subcomponents = Set.copyOf(subcomponents);
+
+ check();
+ }
+
+ private void check()
+ {
+ Set<Signal> allSignals = new HashSet<>();
+ allSignals.addAll(declaration.getIOPorts());
+ allSignals.addAll(internalWires);
+
+ Set<String> usedNames = declaration.getIOPorts().stream().map(IOPort::getName).collect(Collectors.toCollection(HashSet::new));
+
+ for (Wire wire : internalWires)
+ if (!usedNames.add(wire.getName()))
+ throw new IllegalArgumentException("Name occurs twice: " + wire.getName());
+
+ for (Assign assign : assigns)
+ if (!allSignals.contains(assign.getSource()) || !allSignals.contains(assign.getTarget()))
+ throw new IllegalArgumentException("Referenced an unknown signal: " + assign.getSource());
+
+ for (ComponentReference subcomponent : subcomponents)
+ if (!usedNames.add(subcomponent.getName()))
+ throw new IllegalArgumentException("Name occurs twice: " + subcomponent.getName());
+ else if (!subcomponent.getArguments().stream().filter(s -> s.getType() != Type.CONSTANT).allMatch(allSignals::contains))
+ {
+ List<Signal> unknownSignals = new ArrayList<>(subcomponent.getArguments());
+ unknownSignals.removeAll(allSignals);
+ // we know this list contains at least one element
+ throw new IllegalArgumentException("Assigning a signal not in the component: " + unknownSignals.get(0));
+ }
+ }
+
+ public VerilogComponentDeclaration getDeclaration()
+ {
+ return declaration;
+ }
+
+ public Set<Wire> getInternalWires()
+ {
+ return internalWires;
+ }
+
+ public Set<Assign> getAssigns()
+ {
+ return assigns;
+ }
+
+ public Set<ComponentReference> getSubcomponents()
+ {
+ return subcomponents;
+ }
+
+ public String toVerilogCode()
+ {
+ StringBuilder sb = new StringBuilder();
+
+ sb.append("module " + declaration.getID());
+ sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")));
+ sb.append(";\n\n");
+
+ for (Wire wire : internalWires)
+ sb.append(wire.toDeclarationVerilogCode() + "\n");
+ if (!internalWires.isEmpty())
+ sb.append("\n");
+
+ for (Assign assign : assigns)
+ sb.append(assign.toVerilogCode() + "\n");
+ if (!assigns.isEmpty())
+ sb.append("\n");
+
+ for (ComponentReference subcomponent : subcomponents)
+ sb.append(subcomponent.toVerilogCode() + "\n");
+ if (!subcomponents.isEmpty())
+ sb.append("\n");
+
+ sb.append("endmodule\n");
+
+ return sb.toString();
+ }
+
+ @Override
+ public String toString()
+ {
+ return "Implementation[" + declaration.getID() + "]";
+ }
+
+ @Override
+ public int hashCode()
+ {
+ final int prime = 31;
+ int result = 1;
+ result = prime * result + ((assigns == null) ? 0 : assigns.hashCode());
+ result = prime * result + ((declaration == null) ? 0 : declaration.hashCode());
+ result = prime * result + ((internalWires == null) ? 0 : internalWires.hashCode());
+ result = prime * result + ((subcomponents == null) ? 0 : subcomponents.hashCode());
+ return result;
+ }
+
+ @Override
+ public boolean equals(Object obj)
+ {
+ if (this == obj)
+ return true;
+ if (obj == null)
+ return false;
+ if (getClass() != obj.getClass())
+ return false;
+ VerilogComponentImplementation other = (VerilogComponentImplementation) obj;
+ if (assigns == null)
+ {
+ if (other.assigns != null)
+ return false;
+ } else if (!assigns.equals(other.assigns))
+ return false;
+ if (declaration == null)
+ {
+ if (other.declaration != null)
+ return false;
+ } else if (!declaration.equals(other.declaration))
+ return false;
+ if (internalWires == null)
+ {
+ if (other.internalWires != null)
+ return false;
+ } else if (!internalWires.equals(other.internalWires))
+ return false;
+ if (subcomponents == null)
+ {
+ if (other.subcomponents != null)
+ return false;
+ } else if (!subcomponents.equals(other.subcomponents))
+ return false;
+ return true;
+ }
+}
--- /dev/null
+package net.mograsim.logic.model.verilog.model;
+
+public class Wire extends NamedSignal
+{
+ public Wire(String name, int width)
+ {
+ super(Type.WIRE, name, width);
+ }
+
+ public String toDeclarationVerilogCode()
+ {
+ return "wire [" + getWidth() + ":0] " + getName() + ";";
+ }
+}
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<classpath>
+ <classpathentry kind="src" output="target/classes" path="src">
+ <attributes>
+ <attribute name="test" value="true"/>
+ <attribute name="optional" value="true"/>
+ <attribute name="maven.pomderived" value="true"/>
+ </attributes>
+ </classpathentry>
+ <classpathentry kind="con" path="org.eclipse.jdt.launching.JRE_CONTAINER/org.eclipse.jdt.internal.debug.ui.launcher.StandardVMType/JavaSE-11">
+ <attributes>
+ <attribute name="module" value="true"/>
+ <attribute name="maven.pomderived" value="true"/>
+ </attributes>
+ </classpathentry>
+ <classpathentry kind="con" path="org.eclipse.jdt.junit.JUNIT_CONTAINER/5"/>
+ <classpathentry kind="con" path="org.eclipse.pde.core.requiredPlugins"/>
+ <classpathentry kind="output" path="target/classes"/>
+</classpath>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>net.mograsim.logic.model.verilog.tests</name>
+ <comment></comment>
+ <projects>
+ <project>net.mograsim.logic.model.verilog</project>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.jdt.core.javabuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.pde.ManifestBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.pde.SchemaBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.pde.PluginNature</nature>
+ <nature>org.eclipse.jdt.core.javanature</nature>
+ </natures>
+</projectDescription>
--- /dev/null
+eclipse.preferences.version=1
+encoding/<project>=UTF-8
--- /dev/null
+eclipse.preferences.version=1
+line.separator=\n
--- /dev/null
+eclipse.preferences.version=1
+org.eclipse.jdt.core.compiler.annotation.inheritNullAnnotations=disabled
+org.eclipse.jdt.core.compiler.annotation.missingNonNullByDefaultAnnotation=ignore
+org.eclipse.jdt.core.compiler.annotation.nonnull=org.eclipse.jdt.annotation.NonNull
+org.eclipse.jdt.core.compiler.annotation.nonnull.secondary=
+org.eclipse.jdt.core.compiler.annotation.nonnullbydefault=org.eclipse.jdt.annotation.NonNullByDefault
+org.eclipse.jdt.core.compiler.annotation.nonnullbydefault.secondary=
+org.eclipse.jdt.core.compiler.annotation.nullable=org.eclipse.jdt.annotation.Nullable
+org.eclipse.jdt.core.compiler.annotation.nullable.secondary=
+org.eclipse.jdt.core.compiler.annotation.nullanalysis=disabled
+org.eclipse.jdt.core.compiler.codegen.inlineJsrBytecode=enabled
+org.eclipse.jdt.core.compiler.codegen.targetPlatform=11
+org.eclipse.jdt.core.compiler.codegen.unusedLocal=preserve
+org.eclipse.jdt.core.compiler.compliance=11
+org.eclipse.jdt.core.compiler.debug.lineNumber=generate
+org.eclipse.jdt.core.compiler.debug.localVariable=generate
+org.eclipse.jdt.core.compiler.debug.sourceFile=generate
+org.eclipse.jdt.core.compiler.problem.APILeak=warning
+org.eclipse.jdt.core.compiler.problem.annotationSuperInterface=warning
+org.eclipse.jdt.core.compiler.problem.assertIdentifier=error
+org.eclipse.jdt.core.compiler.problem.autoboxing=ignore
+org.eclipse.jdt.core.compiler.problem.comparingIdentical=warning
+org.eclipse.jdt.core.compiler.problem.deadCode=warning
+org.eclipse.jdt.core.compiler.problem.deprecation=warning
+org.eclipse.jdt.core.compiler.problem.deprecationInDeprecatedCode=disabled
+org.eclipse.jdt.core.compiler.problem.deprecationWhenOverridingDeprecatedMethod=enabled
+org.eclipse.jdt.core.compiler.problem.discouragedReference=warning
+org.eclipse.jdt.core.compiler.problem.emptyStatement=warning
+org.eclipse.jdt.core.compiler.problem.enumIdentifier=error
+org.eclipse.jdt.core.compiler.problem.explicitlyClosedAutoCloseable=warning
+org.eclipse.jdt.core.compiler.problem.fallthroughCase=warning
+org.eclipse.jdt.core.compiler.problem.fatalOptionalError=disabled
+org.eclipse.jdt.core.compiler.problem.fieldHiding=ignore
+org.eclipse.jdt.core.compiler.problem.finalParameterBound=warning
+org.eclipse.jdt.core.compiler.problem.finallyBlockNotCompletingNormally=warning
+org.eclipse.jdt.core.compiler.problem.forbiddenReference=error
+org.eclipse.jdt.core.compiler.problem.hiddenCatchBlock=warning
+org.eclipse.jdt.core.compiler.problem.includeNullInfoFromAsserts=disabled
+org.eclipse.jdt.core.compiler.problem.incompatibleNonInheritedInterfaceMethod=warning
+org.eclipse.jdt.core.compiler.problem.incompleteEnumSwitch=warning
+org.eclipse.jdt.core.compiler.problem.indirectStaticAccess=warning
+org.eclipse.jdt.core.compiler.problem.localVariableHiding=ignore
+org.eclipse.jdt.core.compiler.problem.methodWithConstructorName=error
+org.eclipse.jdt.core.compiler.problem.missingDefaultCase=warning
+org.eclipse.jdt.core.compiler.problem.missingDeprecatedAnnotation=info
+org.eclipse.jdt.core.compiler.problem.missingEnumCaseDespiteDefault=disabled
+org.eclipse.jdt.core.compiler.problem.missingHashCodeMethod=warning
+org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotation=warning
+org.eclipse.jdt.core.compiler.problem.missingOverrideAnnotationForInterfaceMethodImplementation=enabled
+org.eclipse.jdt.core.compiler.problem.missingSerialVersion=warning
+org.eclipse.jdt.core.compiler.problem.missingSynchronizedOnInheritedMethod=warning
+org.eclipse.jdt.core.compiler.problem.noEffectAssignment=warning
+org.eclipse.jdt.core.compiler.problem.noImplicitStringConversion=warning
+org.eclipse.jdt.core.compiler.problem.nonExternalizedStringLiteral=ignore
+org.eclipse.jdt.core.compiler.problem.nonnullParameterAnnotationDropped=warning
+org.eclipse.jdt.core.compiler.problem.nonnullTypeVariableFromLegacyInvocation=warning
+org.eclipse.jdt.core.compiler.problem.nullAnnotationInferenceConflict=error
+org.eclipse.jdt.core.compiler.problem.nullReference=warning
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+org.eclipse.jdt.core.formatter.insert_space_before_ellipsis=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_lambda_arrow=insert
+org.eclipse.jdt.core.formatter.insert_space_before_logical_operator=insert
+org.eclipse.jdt.core.formatter.insert_space_before_multiplicative_operator=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_angle_bracket_in_parameterized_type_reference=do not insert
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+org.eclipse.jdt.core.formatter.insert_space_before_opening_angle_bracket_in_type_parameters=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_annotation_type_declaration=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_anonymous_type_declaration=insert
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+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_constructor_declaration=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_enum_constant=insert
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+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_method_declaration=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_brace_in_switch=insert
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+org.eclipse.jdt.core.formatter.insert_space_before_opening_bracket_in_array_allocation_expression=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_bracket_in_array_reference=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_bracket_in_array_type_reference=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_annotation=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_annotation_type_member_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_catch=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_constructor_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_enum_constant=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_for=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_if=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_method_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_method_invocation=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_parenthesized_expression=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_switch=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_synchronized=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_try=insert
+org.eclipse.jdt.core.formatter.insert_space_before_opening_paren_in_while=insert
+org.eclipse.jdt.core.formatter.insert_space_before_parenthesized_expression_in_return=insert
+org.eclipse.jdt.core.formatter.insert_space_before_parenthesized_expression_in_throw=insert
+org.eclipse.jdt.core.formatter.insert_space_before_postfix_operator=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_prefix_operator=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_question_in_conditional=insert
+org.eclipse.jdt.core.formatter.insert_space_before_question_in_wildcard=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_relational_operator=insert
+org.eclipse.jdt.core.formatter.insert_space_before_semicolon=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_semicolon_in_for=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_semicolon_in_try_resources=do not insert
+org.eclipse.jdt.core.formatter.insert_space_before_shift_operator=insert
+org.eclipse.jdt.core.formatter.insert_space_before_string_concatenation=insert
+org.eclipse.jdt.core.formatter.insert_space_before_unary_operator=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_brackets_in_array_type_reference=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_braces_in_array_initializer=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_brackets_in_array_allocation_expression=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_parens_in_annotation_type_member_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_parens_in_constructor_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_parens_in_enum_constant=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_parens_in_method_declaration=do not insert
+org.eclipse.jdt.core.formatter.insert_space_between_empty_parens_in_method_invocation=do not insert
+org.eclipse.jdt.core.formatter.join_lines_in_comments=true
+org.eclipse.jdt.core.formatter.join_wrapped_lines=true
+org.eclipse.jdt.core.formatter.keep_annotation_declaration_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_anonymous_type_declaration_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_code_block_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_else_statement_on_same_line=false
+org.eclipse.jdt.core.formatter.keep_empty_array_initializer_on_one_line=false
+org.eclipse.jdt.core.formatter.keep_enum_constant_declaration_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_enum_declaration_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_if_then_body_block_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_imple_if_on_one_line=false
+org.eclipse.jdt.core.formatter.keep_lambda_body_block_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_loop_body_block_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_method_body_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.keep_simple_do_while_body_on_same_line=false
+org.eclipse.jdt.core.formatter.keep_simple_for_body_on_same_line=false
+org.eclipse.jdt.core.formatter.keep_simple_getter_setter_on_one_line=false
+org.eclipse.jdt.core.formatter.keep_simple_while_body_on_same_line=false
+org.eclipse.jdt.core.formatter.keep_then_statement_on_same_line=false
+org.eclipse.jdt.core.formatter.keep_type_declaration_on_one_line=one_line_never
+org.eclipse.jdt.core.formatter.lineSplit=140
+org.eclipse.jdt.core.formatter.never_indent_block_comments_on_first_column=false
+org.eclipse.jdt.core.formatter.never_indent_line_comments_on_first_column=false
+org.eclipse.jdt.core.formatter.number_of_blank_lines_at_beginning_of_method_body=0
+org.eclipse.jdt.core.formatter.number_of_empty_lines_to_preserve=1
+org.eclipse.jdt.core.formatter.parentheses_positions_in_annotation=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_catch_clause=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_enum_constant_declaration=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_for_statment=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_if_while_statement=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_lambda_declaration=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_method_delcaration=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_method_invocation=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_switch_statement=common_lines
+org.eclipse.jdt.core.formatter.parentheses_positions_in_try_clause=common_lines
+org.eclipse.jdt.core.formatter.put_empty_statement_on_new_line=true
+org.eclipse.jdt.core.formatter.tabulation.char=tab
+org.eclipse.jdt.core.formatter.tabulation.size=4
+org.eclipse.jdt.core.formatter.use_on_off_tags=true
+org.eclipse.jdt.core.formatter.use_tabs_only_for_leading_indentations=false
+org.eclipse.jdt.core.formatter.wrap_before_additive_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_assignment_operator=false
+org.eclipse.jdt.core.formatter.wrap_before_bitwise_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_conditional_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_logical_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_multiplicative_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_or_operator_multicatch=true
+org.eclipse.jdt.core.formatter.wrap_before_relational_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_shift_operator=true
+org.eclipse.jdt.core.formatter.wrap_before_string_concatenation=true
+org.eclipse.jdt.core.formatter.wrap_outer_expressions_when_nested=true
+org.eclipse.jdt.core.javaFormatter=org.eclipse.jdt.core.defaultJavaFormatter
--- /dev/null
+eclipse.preferences.version=1
+editor_save_participant_org.eclipse.jdt.ui.postsavelistener.cleanup=true
+formatter_profile=_MoGraSim
+formatter_settings_version=16
+sp_cleanup.add_default_serial_version_id=true
+sp_cleanup.add_generated_serial_version_id=false
+sp_cleanup.add_missing_annotations=true
+sp_cleanup.add_missing_deprecated_annotations=true
+sp_cleanup.add_missing_methods=false
+sp_cleanup.add_missing_nls_tags=false
+sp_cleanup.add_missing_override_annotations=true
+sp_cleanup.add_missing_override_annotations_interface_methods=true
+sp_cleanup.add_serial_version_id=false
+sp_cleanup.always_use_blocks=true
+sp_cleanup.always_use_parentheses_in_expressions=false
+sp_cleanup.always_use_this_for_non_static_field_access=false
+sp_cleanup.always_use_this_for_non_static_method_access=false
+sp_cleanup.convert_functional_interfaces=false
+sp_cleanup.convert_to_enhanced_for_loop=false
+sp_cleanup.correct_indentation=false
+sp_cleanup.format_source_code=true
+sp_cleanup.format_source_code_changes_only=false
+sp_cleanup.insert_inferred_type_arguments=false
+sp_cleanup.make_local_variable_final=true
+sp_cleanup.make_parameters_final=false
+sp_cleanup.make_private_fields_final=true
+sp_cleanup.make_type_abstract_if_missing_method=false
+sp_cleanup.make_variable_declarations_final=false
+sp_cleanup.never_use_blocks=false
+sp_cleanup.never_use_parentheses_in_expressions=true
+sp_cleanup.on_save_use_additional_actions=false
+sp_cleanup.organize_imports=false
+sp_cleanup.qualify_static_field_accesses_with_declaring_class=false
+sp_cleanup.qualify_static_member_accesses_through_instances_with_declaring_class=true
+sp_cleanup.qualify_static_member_accesses_through_subtypes_with_declaring_class=true
+sp_cleanup.qualify_static_member_accesses_with_declaring_class=false
+sp_cleanup.qualify_static_method_accesses_with_declaring_class=false
+sp_cleanup.remove_private_constructors=true
+sp_cleanup.remove_redundant_modifiers=false
+sp_cleanup.remove_redundant_semicolons=false
+sp_cleanup.remove_redundant_type_arguments=false
+sp_cleanup.remove_trailing_whitespaces=false
+sp_cleanup.remove_trailing_whitespaces_all=true
+sp_cleanup.remove_trailing_whitespaces_ignore_empty=false
+sp_cleanup.remove_unnecessary_casts=true
+sp_cleanup.remove_unnecessary_nls_tags=false
+sp_cleanup.remove_unused_imports=false
+sp_cleanup.remove_unused_local_variables=false
+sp_cleanup.remove_unused_private_fields=true
+sp_cleanup.remove_unused_private_members=false
+sp_cleanup.remove_unused_private_methods=true
+sp_cleanup.remove_unused_private_types=true
+sp_cleanup.sort_members=false
+sp_cleanup.sort_members_all=false
+sp_cleanup.use_anonymous_class_creation=false
+sp_cleanup.use_blocks=false
+sp_cleanup.use_blocks_only_for_return_and_throw=false
+sp_cleanup.use_lambda=true
+sp_cleanup.use_parentheses_in_expressions=false
+sp_cleanup.use_this_for_non_static_field_access=false
+sp_cleanup.use_this_for_non_static_field_access_only_if_necessary=true
+sp_cleanup.use_this_for_non_static_method_access=false
+sp_cleanup.use_this_for_non_static_method_access_only_if_necessary=true
--- /dev/null
+Manifest-Version: 1.0
+Bundle-ManifestVersion: 2
+Bundle-Name: Verilog Tests
+Bundle-SymbolicName: net.mograsim.logic.model.verilog.tests;singleton:=true
+Bundle-Version: 0.1.4.qualifier
+Bundle-Vendor: Mograsim Team
+Fragment-Host: net.mograsim.logic.model.verilog;bundle-version="0.1.4"
+Automatic-Module-Name: net.mograsim.logic.model.verilog.tests
+Bundle-RequiredExecutionEnvironment: JavaSE-11
+Require-Bundle: org.junit;bundle-version="4.12.0",
+ org.junit.jupiter.api;bundle-version="5.4.0";visibility:=reexport,
+ org.junit.jupiter.params;bundle-version="5.4.0";visibility:=reexport,
+ org.opentest4j;bundle-version="1.1.1";visibility:=reexport,
+ net.mograsim.logic.model.am2900;bundle-version="0.1.4"
--- /dev/null
+source.. = src/
+bin.includes = META-INF/,\
+ .
--- /dev/null
+package net.mograsim.logic.model.verilog.examples;
+
+import java.io.IOException;
+import java.nio.file.Files;
+import java.nio.file.Path;
+import java.nio.file.Paths;
+import java.util.Scanner;
+import java.util.Set;
+import java.util.stream.Collectors;
+import java.util.stream.Stream;
+
+import com.google.gson.JsonElement;
+
+import net.mograsim.logic.core.types.BitVector;
+import net.mograsim.logic.model.am2900.Am2900Loader;
+import net.mograsim.logic.model.am2900.components.ModelAm2900MPROM;
+import net.mograsim.logic.model.am2900.components.ModelAm2900MainMemory;
+import net.mograsim.logic.model.am2900.components.ModelAm2900MicroInstructionMemory;
+import net.mograsim.logic.model.model.LogicModelModifiable;
+import net.mograsim.logic.model.model.components.ModelComponent;
+import net.mograsim.logic.model.model.components.Orientation;
+import net.mograsim.logic.model.model.components.atomic.ModelBitDisplay;
+import net.mograsim.logic.model.model.components.atomic.ModelClock;
+import net.mograsim.logic.model.model.components.atomic.ModelClock.ModelClockParams;
+import net.mograsim.logic.model.model.components.atomic.ModelFixedOutput;
+import net.mograsim.logic.model.model.components.atomic.ModelNandGate;
+import net.mograsim.logic.model.model.components.atomic.ModelSplitter;
+import net.mograsim.logic.model.model.components.atomic.ModelSplitter.SplitterParams;
+import net.mograsim.logic.model.model.components.atomic.ModelTextComponent;
+import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer;
+import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer.ModelTriStateBufferParams;
+import net.mograsim.logic.model.model.wires.ModelWireCrossPoint;
+import net.mograsim.logic.model.serializing.IdentifyParams;
+import net.mograsim.logic.model.serializing.IndirectModelComponentCreator;
+import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogComponentDeclarationMapping;
+import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogConverter;
+import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation;
+
+public class ExportAm2900
+{
+ public static void main(String[] args) throws IOException
+ {
+ Am2900Loader.setup();
+ try (Scanner sysin = new Scanner(System.in))
+ {
+ System.out.print("Directory to export Verilog into >");
+ Path target = Paths.get(sysin.nextLine());
+ if (!Files.exists(target))
+ Files.createDirectories(target);
+ else if (!Files.isDirectory(target))
+ throw new IllegalArgumentException("Target exists and is not a directory");
+
+ System.out.print("Component ID to serialize recursively >");
+ String rootComponentID = sysin.nextLine();
+ {
+ if (!Files.exists(target))
+ Files.createDirectories(target);
+ else if (!Files.isDirectory(target))
+ throw new IllegalArgumentException("Target exists and is not a directory");
+
+ LogicModelModifiable model = new LogicModelModifiable();
+
+ Set<ModelComponentToVerilogComponentDeclarationMapping> atomicComponentMappings = Stream.of(//
+ new ModelNandGate(model, 1), //
+ new ModelFixedOutput(model, BitVector.SINGLE_0, null), //
+ new ModelFixedOutput(model, BitVector.SINGLE_1, null), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.RIGHT)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.RIGHT_ALT)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(1, Orientation.DOWN)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(4, Orientation.RIGHT)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(12, Orientation.RIGHT_ALT)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(12, Orientation.DOWN)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.LEFT)), //
+ new ModelTriStateBuffer(model, new ModelTriStateBufferParams(16, Orientation.RIGHT_ALT)), //
+ new ModelWireCrossPoint(model, 1), //
+ new ModelWireCrossPoint(model, 2), //
+ new ModelWireCrossPoint(model, 4), //
+ new ModelWireCrossPoint(model, 9), //
+ new ModelWireCrossPoint(model, 12), //
+ new ModelWireCrossPoint(model, 16), //
+ new ModelSplitter(model, new SplitterParams(2, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(2, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(2, Orientation.UP)), //
+ new ModelSplitter(model, new SplitterParams(2, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(3, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(3, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(3, Orientation.UP)), //
+ new ModelSplitter(model, new SplitterParams(3, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(3, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(4, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(4, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(4, Orientation.UP)), //
+ new ModelSplitter(model, new SplitterParams(4, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(4, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(5, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(5, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(6, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(6, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(6, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(6, Orientation.UP)), //
+ new ModelSplitter(model, new SplitterParams(6, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(8, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(8, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(9, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(9, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(12, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(12, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(12, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(12, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(13, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(13, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(16, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(16, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(16, Orientation.UP)), //
+ new ModelSplitter(model, new SplitterParams(16, Orientation.DOWN)), //
+ new ModelSplitter(model, new SplitterParams(16, Orientation.DOWN_ALT)), //
+ new ModelSplitter(model, new SplitterParams(80, Orientation.LEFT)), //
+ new ModelSplitter(model, new SplitterParams(80, Orientation.RIGHT)), //
+ new ModelSplitter(model, new SplitterParams(80, Orientation.UP_ALT)), //
+ new ModelClock(model, new ModelClockParams(7000, Orientation.RIGHT)), //
+ new ModelTextComponent(model, "A bus"), //
+ new ModelTextComponent(model, "MPM addr"), //
+ new ModelTextComponent(model, "D bus"), //
+ new ModelAm2900MainMemory(model, null), //
+ new ModelAm2900MPROM(model, null), //
+ new ModelAm2900MicroInstructionMemory(model, null), //
+ new ModelBitDisplay(model, 12), //
+ new ModelBitDisplay(model, 16)//
+ ).map(c ->
+ {
+ String id = c.getIDForSerializing(new IdentifyParams());
+ JsonElement params = c.getParamsForSerializingJSON(new IdentifyParams());
+ ModelComponentToVerilogComponentDeclarationMapping generateCanonicalDeclarationMapping = ModelComponentToVerilogConverter
+ .generateCanonicalDeclarationMapping(c, id, params, ModelComponentToVerilogConverter
+ .sanitizeVerilogID("mgs_" + id + (params.isJsonNull() ? "" : "_" + params)));
+ return generateCanonicalDeclarationMapping;
+ }).collect(Collectors.toSet());
+
+ ModelComponent root = IndirectModelComponentCreator.createComponent(model, rootComponentID);
+ Set<VerilogComponentImplementation> convertResult = ModelComponentToVerilogConverter.convert(atomicComponentMappings,
+ Set.of(root), "mgs_conv_");
+ for (VerilogComponentImplementation convertedComponent : convertResult)
+ Files.writeString(target.resolve(convertedComponent.getDeclaration().getID() + ".v"),
+ convertedComponent.toVerilogCode());
+ }
+ }
+ }
+}
projects / Mograsim.git / commitdiff