net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/CoreXorGate.java

   1 package net.mograsim.logic.core.components.gates;
   2
   3 import net.mograsim.logic.core.timeline.Timeline;
   4 import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
   5 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
   6 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
   7
   8 /**
   9  * Outputs 1 when the number of 1 inputs is odd.
  10  *
  11  * @author Fabian Stemmler
  12  */
  13 public class CoreXorGate extends MultiInputCoreGate
  14 {
  15         public CoreXorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)
  16         {
  17                 super(timeline, processTime, BitVectorMutator::xor, out, in);
  18         }
  19
  20 }