4ba4b1958479a5d2b92438a8bdbc82fa384d26be
[Mograsim.git] / net.mograsim.logic.model.am2900 / components / net / mograsim / logic / model / am2900 / components / fulladder.json
1 {
2   "width": 35.0,
3   "height": 30.0,
4   "interfacePins": [
5     {
6       "location": {
7         "x": 0.0,
8         "y": 5.0
9       },
10       "name": "A",
11       "logicWidth": 1,
12       "usage": "INPUT"
13     },
14     {
15       "location": {
16         "x": 0.0,
17         "y": 15.0
18       },
19       "name": "B",
20       "logicWidth": 1,
21       "usage": "INPUT"
22     },
23     {
24       "location": {
25         "x": 0.0,
26         "y": 25.0
27       },
28       "name": "C",
29       "logicWidth": 1,
30       "usage": "INPUT"
31     },
32     {
33       "location": {
34         "x": 35.0,
35         "y": 5.0
36       },
37       "name": "Y",
38       "logicWidth": 1,
39       "usage": "OUTPUT"
40     },
41     {
42       "location": {
43         "x": 35.0,
44         "y": 15.0
45       },
46       "name": "Z",
47       "logicWidth": 1,
48       "usage": "OUTPUT"
49     }
50   ],
51   "innerScale": 0.4,
52   "submodel": {
53     "components": [
54       {
55         "id": "NandGate",
56         "name": "NandGate#0",
57         "pos": {
58           "x": 57.5,
59           "y": 40.0
60         },
61         "params": 1
62       },
63       {
64         "id": "halfadder",
65         "name": "halfadder#0",
66         "pos": {
67           "x": 5.0,
68           "y": 40.0
69         }
70       },
71       {
72         "id": "halfadder",
73         "name": "halfadder#1",
74         "pos": {
75           "x": 45.0,
76           "y": 7.5
77         }
78       }
79     ],
80     "wires": [
81       {
82         "pin1": {
83           "compName": "_submodelinterface",
84           "pinName": "A"
85         },
86         "pin2": {
87           "compName": "halfadder#1",
88           "pinName": "A"
89         },
90         "name": "unnamedWire#0",
91         "path": []
92       },
93       {
94         "pin1": {
95           "compName": "_submodelinterface",
96           "pinName": "B"
97         },
98         "pin2": {
99           "compName": "halfadder#0",
100           "pinName": "A"
101         },
102         "name": "unnamedWire#1"
103       },
104       {
105         "pin1": {
106           "compName": "_submodelinterface",
107           "pinName": "C"
108         },
109         "pin2": {
110           "compName": "halfadder#0",
111           "pinName": "B"
112         },
113         "name": "unnamedWire#2"
114       },
115       {
116         "pin1": {
117           "compName": "halfadder#0",
118           "pinName": "Y"
119         },
120         "pin2": {
121           "compName": "halfadder#1",
122           "pinName": "B"
123         },
124         "name": "unnamedWire#3"
125       },
126       {
127         "pin1": {
128           "compName": "halfadder#0",
129           "pinName": "_Z"
130         },
131         "pin2": {
132           "compName": "NandGate#0",
133           "pinName": "B"
134         },
135         "name": "unnamedWire#4",
136         "path": []
137       },
138       {
139         "pin1": {
140           "compName": "halfadder#1",
141           "pinName": "Y"
142         },
143         "pin2": {
144           "compName": "_submodelinterface",
145           "pinName": "Y"
146         },
147         "name": "unnamedWire#5",
148         "path": []
149       },
150       {
151         "pin1": {
152           "compName": "halfadder#1",
153           "pinName": "_Z"
154         },
155         "pin2": {
156           "compName": "NandGate#0",
157           "pinName": "A"
158         },
159         "name": "unnamedWire#6",
160         "path": [
161           {
162             "x": 82.5,
163             "y": 22.5
164           },
165           {
166             "x": 82.5,
167             "y": 35.0
168           },
169           {
170             "x": 52.5,
171             "y": 35.0
172           },
173           {
174             "x": 52.5,
175             "y": 45.0
176           }
177         ]
178       },
179       {
180         "pin1": {
181           "compName": "NandGate#0",
182           "pinName": "Y"
183         },
184         "pin2": {
185           "compName": "_submodelinterface",
186           "pinName": "Z"
187         },
188         "name": "unnamedWire#7"
189       }
190     ],
191     "version": "0.1.1"
192   },
193   "symbolRendererSnippetID": "simpleRectangularLike",
194   "symbolRendererParams": {
195     "centerText": "fulladder",
196     "centerTextHeight": 5.0,
197     "horizontalComponentCenter": 17.5,
198     "pinLabelHeight": 3.5,
199     "pinLabelMargin": 0.5
200   },
201   "outlineRendererSnippetID": "default",
202   "highLevelStateHandlerSnippetID": "default",
203   "version": "0.1.5"
204 }