Fixed nand and nor gate to work with more than two inputs

diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
index 6b183e3..9cea197 100644 (file)
--- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
@@ -15,6 +15,7 @@ public abstract class MultiInputGate extends BasicComponent
        protected ReadWriteEnd out;
        protected final int length;
        protected MutationOperation op;
+       protected boolean invert = false;
 
        protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in)
        {
@@ -33,6 +34,12 @@ public abstract class MultiInputGate extends BasicComponent
                this.out = out;
        }
 
+       protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in)
+       {
+               this(timeline, processTime, op, out, in);
+               this.invert = invert;
+       }
+
        @Override
        public List<ReadEnd> getAllInputs()
        {
@@ -51,6 +58,6 @@ public abstract class MultiInputGate extends BasicComponent
                BitVectorMutator mutator = BitVectorMutator.empty();
                for (ReadEnd w : in)
                        op.apply(mutator, w.getValues());
-               out.feedSignals(mutator.get());
+               out.feedSignals(invert ? mutator.get().not() : mutator.get());
        }
 }

diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java
index ff8f790..0e40648 100644 (file)
--- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NandGate.java
@@ -9,6 +9,6 @@ public class NandGate extends MultiInputGate
 {
        public NandGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)
        {
-               super(timeline, processTime, BitVectorMutator::nand, out, in);
+               super(timeline, processTime, BitVectorMutator::and, true, out, in);
        }
 }

diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java
index cfadf46..5f6e185 100644 (file)
--- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NorGate.java
@@ -9,6 +9,6 @@ public class NorGate extends MultiInputGate
 {
        public NorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)
        {
-               super(timeline, processTime, BitVectorMutator::nor, out, in);
+               super(timeline, processTime, BitVectorMutator::or, true, out, in);
        }
 }

diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/tests/ComponentTest.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/tests/ComponentTest.java
index b015d21..38d1b7c 100644 (file)
--- a/net.mograsim.logic.core/src/net/mograsim/logic/core/tests/ComponentTest.java
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/tests/ComponentTest.java
@@ -15,6 +15,8 @@ import net.mograsim.logic.core.components.Mux;
 import net.mograsim.logic.core.components.Splitter;
 import net.mograsim.logic.core.components.TriStateBuffer;
 import net.mograsim.logic.core.components.gates.AndGate;
+import net.mograsim.logic.core.components.gates.NandGate;
+import net.mograsim.logic.core.components.gates.NorGate;
 import net.mograsim.logic.core.components.gates.NotGate;
 import net.mograsim.logic.core.components.gates.OrGate;
 import net.mograsim.logic.core.components.gates.XorGate;
@@ -207,6 +209,36 @@ class ComponentTest
                assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ONE);
        }
 
+       @Test
+       void nandTest()
+       {
+               t.reset();
+               Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1);
+               new NandGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
+               b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
+               c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
+
+               t.executeAll();
+
+               assertBitArrayEquals(d.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ONE);
+       }
+
+       @Test
+       void norTest()
+       {
+               t.reset();
+               Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1), d = new Wire(t, 4, 1);
+               new NorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());
+               a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
+               b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
+               c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
+
+               t.executeAll();
+
+               assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ZERO, Bit.ONE, Bit.ZERO);
+       }
+
        @Test
        void xorTest()
        {