1 package era.mi.logic.components.gates;
3 import era.mi.logic.types.BitVector.BitVectorMutator;
4 import era.mi.logic.wires.Wire.WireEnd;
6 public class AndGate extends MultiInputGate
8 public AndGate(int processTime, WireEnd out, WireEnd... in)
10 super(processTime, BitVectorMutator::and, out, in);