1 package era.mi.logic.components.gates;
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3 import era.mi.logic.types.BitVector.BitVectorMutator;
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4 import era.mi.logic.wires.Wire.ReadEnd;
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5 import era.mi.logic.wires.Wire.ReadWriteEnd;
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7 public class AndGate extends MultiInputGate
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9 public AndGate(int processTime, ReadWriteEnd out, ReadEnd... in)
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11 super(processTime, BitVectorMutator::and, out, in);
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