1 package net.mograsim.logic.core.components.memory;
5 import net.mograsim.logic.core.components.BasicComponent;
6 import net.mograsim.logic.core.timeline.Timeline;
7 import net.mograsim.logic.core.types.Bit;
8 import net.mograsim.logic.core.types.BitVector;
9 import net.mograsim.logic.core.wires.Wire.ReadEnd;
10 import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
13 * A memory component that only allows access to words of a specific length
15 public class WordAddressableMemoryComponent extends BasicComponent
17 private final WordAddressableMemory memory;
18 private final static Bit read = Bit.ONE;
20 private ReadWriteEnd data;
21 private ReadEnd rWBit, address;
24 * @param data The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
26 * @param rWBit The value of the 0th bit dictates the mode: 0: Write, 1: Read
27 * @param address The bits of this ReadEnd address the memory cell to read/write
29 public WordAddressableMemoryComponent(Timeline timeline, int processTime, long minimalAddress, long maximalAddress, ReadWriteEnd data,
30 ReadEnd rWBit, ReadEnd address)
32 super(timeline, processTime);
35 this.address = address;
36 data.registerObserver(this);
37 rWBit.registerObserver(this);
38 address.registerObserver(this);
40 memory = new WordAddressableMemory(data.length(), minimalAddress, maximalAddress);
44 protected void compute()
46 if (!address.hasNumericValue())
48 if (read.equals(rWBit.getValue()))
49 data.feedSignals(BitVector.of(Bit.U, data.length()));
54 long addressed = address.getUnsignedValue();
55 if (read.equals(rWBit.getValue()))
56 data.feedSignals(memory.getCell(addressed));
60 memory.setCell(addressed, data.getValues());
65 public List<ReadEnd> getAllInputs()
67 return List.of(data, rWBit, address);
71 public List<ReadWriteEnd> getAllOutputs()