1 package net.mograsim.logic.core.components.gates;
3 import net.mograsim.logic.core.timeline.Timeline;
4 import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
5 import net.mograsim.logic.core.wires.Wire.ReadEnd;
6 import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
8 public class AndGate extends MultiInputGate
10 public AndGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)
12 super(timeline, processTime, BitVectorMutator::and, out, in);