1 package net.mograsim.logic.core.components.gates;
5 import net.mograsim.logic.core.components.BasicCoreComponent;
6 import net.mograsim.logic.core.timeline.Timeline;
7 import net.mograsim.logic.core.timeline.TimelineEventHandler;
8 import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
9 import net.mograsim.logic.core.types.MutationOperation;
10 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
11 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
13 public abstract class MultiInputCoreGate extends BasicCoreComponent
15 protected ReadEnd[] in;
16 protected ReadWriteEnd out;
17 protected final int width;
18 protected MutationOperation op;
19 protected boolean invert = false;
21 protected MultiInputCoreGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in)
23 super(timeline, processTime);
28 throw new IllegalArgumentException(String.format("Cannot create gate with %d wires.", in.length));
31 if (w.width() != width)
32 throw new IllegalArgumentException("All wires connected to the gate must be of uniform length.");
33 w.registerObserver(this);
38 protected MultiInputCoreGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in)
40 this(timeline, processTime, op, out, in);
45 public List<ReadEnd> getAllInputs()
51 public List<ReadWriteEnd> getAllOutputs()
57 public TimelineEventHandler compute()
59 BitVectorMutator mutator = BitVectorMutator.empty();
61 op.apply(mutator, w.getValues());
62 return e -> out.feedSignals(invert ? mutator.toBitVector().not() : mutator.toBitVector());