1 package net.mograsim.logic.core.components.gates;
5 import net.mograsim.logic.core.components.BasicComponent;
6 import net.mograsim.logic.core.timeline.Timeline;
7 import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
8 import net.mograsim.logic.core.types.MutationOperation;
9 import net.mograsim.logic.core.wires.Wire.ReadEnd;
10 import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
12 public abstract class MultiInputGate extends BasicComponent
14 protected ReadEnd[] in;
15 protected ReadWriteEnd out;
16 protected final int width;
17 protected MutationOperation op;
18 protected boolean invert = false;
20 protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in)
22 super(timeline, processTime);
27 throw new IllegalArgumentException(String.format("Cannot create gate with %d wires.", in.length));
30 if (w.width() != width)
31 throw new IllegalArgumentException("All wires connected to the gate must be of uniform length.");
32 w.registerObserver(this);
37 protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in)
39 this(timeline, processTime, op, out, in);
44 public List<ReadEnd> getAllInputs()
50 public List<ReadWriteEnd> getAllOutputs()
56 protected void compute()
58 BitVectorMutator mutator = BitVectorMutator.empty();
60 op.apply(mutator, w.getValues());
61 out.feedSignals(invert ? mutator.toBitVector().not() : mutator.toBitVector());