net.mograsim.logic.model.editor/components/GUI_rsLatch.json

   1 mograsim version: 0.1.3
   2 {
   3   "width": 35.0,
   4   "height": 20.0,
   5   "interfacePins": [
   6     {
   7       "location": {
   8         "x": 35.0,
   9         "y": 5.0
  10       },
  11       "name": "Q",
  12       "logicWidth": 1
  13     },
  14     {
  15       "location": {
  16         "x": 35.0,
  17         "y": 15.0
  18       },
  19       "name": "_Q",
  20       "logicWidth": 1
  21     },
  22     {
  23       "location": {
  24         "x": 0.0,
  25         "y": 15.0
  26       },
  27       "name": "_R",
  28       "logicWidth": 1
  29     },
  30     {
  31       "location": {
  32         "x": 0.0,
  33         "y": 5.0
  34       },
  35       "name": "_S",
  36       "logicWidth": 1
  37     }
  38   ],
  39   "submodel": {
  40     "innerScale": 0.4,
  41     "subComps": [
  42       {
  43         "id": "GUINandGate",
  44         "name": "GUINandGate#1",
  45         "pos": {
  46           "x": 40.0,
  47           "y": 12.5
  48         },
  49         "params": 1
  50       },
  51       {
  52         "id": "GUINandGate",
  53         "name": "GUINandGate#0",
  54         "pos": {
  55           "x": 10.0,
  56           "y": 7.5
  57         },
  58         "params": 1
  59       },
  60       {
  61         "id": "WireCrossPoint",
  62         "name": "WireCrossPoint#1",
  63         "pos": {
  64           "x": 64.0,
  65           "y": 36.5
  66         },
  67         "params": 1
  68       },
  69       {
  70         "id": "WireCrossPoint",
  71         "name": "WireCrossPoint#0",
  72         "pos": {
  73           "x": 34.0,
  74           "y": 16.5
  75         },
  76         "params": 1
  77       }
  78     ],
  79     "innerWires": [
  80       {
  81         "pin1": {
  82           "compName": "WireCrossPoint#0",
  83           "pinName": ""
  84         },
  85         "pin2": {
  86           "compName": "_submodelinterface",
  87           "pinName": "Q"
  88         },
  89         "name": "q",
  90         "path": [
  91           {
  92             "x": 35.0,
  93             "y": 17.5
  94           },
  95           {
  96             "x": 35.0,
  97             "y": 7.5
  98           },
  99           {
 100             "x": 65.0,
 101             "y": 7.5
 102           },
 103           {
 104             "x": 65.0,
 105             "y": 12.5
 106           }
 107         ]
 108       },
 109       {
 110         "pin1": {
 111           "compName": "WireCrossPoint#1",
 112           "pinName": ""
 113         },
 114         "pin2": {
 115           "compName": "_submodelinterface",
 116           "pinName": "_Q"
 117         },
 118         "name": "_q",
 119         "path": []
 120       },
 121       {
 122         "pin1": {
 123           "compName": "_submodelinterface",
 124           "pinName": "_R"
 125         },
 126         "pin2": {
 127           "compName": "GUINandGate#1",
 128           "pinName": "B"
 129         },
 130         "name": "unnamedWire#1",
 131         "path": [
 132           {
 133             "x": 35.0,
 134             "y": 37.5
 135           },
 136           {
 137             "x": 35.0,
 138             "y": 27.5
 139           }
 140         ]
 141       },
 142       {
 143         "pin1": {
 144           "compName": "_submodelinterface",
 145           "pinName": "_S"
 146         },
 147         "pin2": {
 148           "compName": "GUINandGate#0",
 149           "pinName": "A"
 150         },
 151         "name": "unnamedWire#0",
 152         "path": []
 153       },
 154       {
 155         "pin1": {
 156           "compName": "WireCrossPoint#1",
 157           "pinName": ""
 158         },
 159         "pin2": {
 160           "compName": "GUINandGate#0",
 161           "pinName": "B"
 162         },
 163         "name": "unnamedWire#5",
 164         "path": [
 165           {
 166             "x": 65.0,
 167             "y": 42.5
 168           },
 169           {
 170             "x": 5.0,
 171             "y": 42.5
 172           },
 173           {
 174             "x": 5.0,
 175             "y": 22.5
 176           }
 177         ]
 178       },
 179       {
 180         "pin1": {
 181           "compName": "WireCrossPoint#0",
 182           "pinName": ""
 183         },
 184         "pin2": {
 185           "compName": "GUINandGate#1",
 186           "pinName": "A"
 187         },
 188         "name": "unnamedWire#4",
 189         "path": []
 190       },
 191       {
 192         "pin1": {
 193           "compName": "GUINandGate#1",
 194           "pinName": "Y"
 195         },
 196         "pin2": {
 197           "compName": "WireCrossPoint#1",
 198           "pinName": ""
 199         },
 200         "name": "unnamedWire#3",
 201         "path": [
 202           {
 203             "x": 65.0,
 204             "y": 22.5
 205           }
 206         ]
 207       },
 208       {
 209         "pin1": {
 210           "compName": "GUINandGate#0",
 211           "pinName": "Y"
 212         },
 213         "pin2": {
 214           "compName": "WireCrossPoint#0",
 215           "pinName": ""
 216         },
 217         "name": "unnamedWire#2",
 218         "path": []
 219       }
 220     ]
 221   },
 222   "symbolRendererSnippetID": "class:net.mograsim.logic.model.snippets.symbolrenderers.SimpleRectangularLikeSymbolRenderer",
 223   "symbolRendererParams": {
 224     "centerText": "_rsLatch",
 225     "centerTextHeight": 5.0,
 226     "horizontalComponentCenter": 17.5,
 227     "pinLabelHeight": 3.5,
 228     "pinLabelMargin": 0.5
 229   },
 230   "outlineRendererSnippetID": "class:net.mograsim.logic.model.snippets.outlinerenderers.DefaultOutlineRenderer",
 231   "highLevelStateHandlerSnippetID": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.StandardHighLevelStateHandler",
 232   "highLevelStateHandlerParams": {
 233     "subcomponentHighLevelStates": {},
 234     "atomicHighLevelStates": {
 235       "q": {
 236         "id": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.atomic.WireForcingAtomicHighLevelStateHandler",
 237         "params": {
 238           "wiresToForce": [
 239             "q"
 240           ],
 241           "wiresToForceInverted": [
 242             "_q"
 243           ]
 244         }
 245       }
 246     }
 247   }
 248 }