1 package net.mograsim.logic.ui.modeladapter.componentadapters;
5 import net.mograsim.logic.core.components.gates.AndGate;
6 import net.mograsim.logic.core.components.gates.NotGate;
7 import net.mograsim.logic.core.timeline.Timeline;
8 import net.mograsim.logic.core.wires.Wire;
9 import net.mograsim.logic.ui.model.components.AtomicAm2901NANDBased;
10 import net.mograsim.logic.ui.model.wires.Pin;
11 import net.mograsim.logic.ui.modeladapter.LogicModelParameters;
13 public class AtomicAm2901NANDBasedAdapter implements ComponentAdapter<AtomicAm2901NANDBased>
16 public Class<AtomicAm2901NANDBased> getSupportedClass()
18 return AtomicAm2901NANDBased.class;
22 public void createAndLinkComponent(Timeline timeline, LogicModelParameters params, AtomicAm2901NANDBased guiComponent,
23 Map<Pin, Wire> logicWiresPerPin)
25 Wire w00 = logicWiresPerPin.get(guiComponent.getPin("I8"));
26 Wire w01 = logicWiresPerPin.get(guiComponent.getPin("I7"));
27 Wire w02 = logicWiresPerPin.get(guiComponent.getPin("I6"));
28 Wire w03 = logicWiresPerPin.get(guiComponent.getPin("I5"));
29 Wire w04 = logicWiresPerPin.get(guiComponent.getPin("I4"));
30 Wire w05 = logicWiresPerPin.get(guiComponent.getPin("I3"));
31 Wire w06 = logicWiresPerPin.get(guiComponent.getPin("I2"));
32 Wire w07 = logicWiresPerPin.get(guiComponent.getPin("I1"));
33 Wire w08 = logicWiresPerPin.get(guiComponent.getPin("I0"));
34 Wire w09 = logicWiresPerPin.get(guiComponent.getPin("C"));
35 Wire w10 = logicWiresPerPin.get(guiComponent.getPin("Cn"));
36 Wire w11 = logicWiresPerPin.get(guiComponent.getPin("D1"));
37 Wire w12 = logicWiresPerPin.get(guiComponent.getPin("D2"));
38 Wire w13 = logicWiresPerPin.get(guiComponent.getPin("D3"));
39 Wire w14 = logicWiresPerPin.get(guiComponent.getPin("D4"));
40 Wire w15 = logicWiresPerPin.get(guiComponent.getPin("A0"));
41 Wire w16 = logicWiresPerPin.get(guiComponent.getPin("A1"));
42 Wire w17 = logicWiresPerPin.get(guiComponent.getPin("A2"));
43 Wire w18 = logicWiresPerPin.get(guiComponent.getPin("A3"));
44 Wire w19 = logicWiresPerPin.get(guiComponent.getPin("B0"));
45 Wire w20 = logicWiresPerPin.get(guiComponent.getPin("B1"));
46 Wire w21 = logicWiresPerPin.get(guiComponent.getPin("B2"));
47 Wire w22 = logicWiresPerPin.get(guiComponent.getPin("B3"));
48 Wire w23 = logicWiresPerPin.get(guiComponent.getPin("IRAMn"));
49 Wire w24 = logicWiresPerPin.get(guiComponent.getPin("IRAMn+3"));
50 Wire w25 = logicWiresPerPin.get(guiComponent.getPin("IQn"));
51 Wire w26 = logicWiresPerPin.get(guiComponent.getPin("IQn+3"));
52 Wire w27 = logicWiresPerPin.get(guiComponent.getPin("Y1"));
53 Wire w28 = logicWiresPerPin.get(guiComponent.getPin("Y2"));
54 Wire w29 = logicWiresPerPin.get(guiComponent.getPin("Y3"));
55 Wire w30 = logicWiresPerPin.get(guiComponent.getPin("Y4"));
56 Wire w31 = logicWiresPerPin.get(guiComponent.getPin("F=0"));
57 Wire w32 = logicWiresPerPin.get(guiComponent.getPin("Cn+4"));
58 Wire w33 = logicWiresPerPin.get(guiComponent.getPin("OVR"));
59 Wire w34 = logicWiresPerPin.get(guiComponent.getPin("F3_ORAMn+3"));
60 Wire w35 = logicWiresPerPin.get(guiComponent.getPin("ORAMn"));
61 Wire w36 = logicWiresPerPin.get(guiComponent.getPin("OQn"));
62 Wire w37 = logicWiresPerPin.get(guiComponent.getPin("OQn+3"));
64 createAm2901(timeline, params, w00, w01, w02, w03, w04, w05, w06, w07, w08, w09, w10, w11, w12, w13, w14, w15, w16, w17, w18, w19,
65 w20, w21, w22, w23, w24, w25, w26, w27, w28, w29, w30, w31, w32, w33, w34, w35, w36, w37);
68 private static void create_rsLatch(Timeline timeline, LogicModelParameters params, Wire _S, Wire _R, Wire Q, Wire _Q)
70 createNand(timeline, params, _S, _Q, Q);
71 createNand(timeline, params, _R, Q, _Q);
74 private static void createAm2901(Timeline timeline, LogicModelParameters params, Wire I8, Wire I7, Wire I6, Wire I5, Wire I4, Wire I3,
75 Wire I2, Wire I1, Wire I0, Wire C, Wire Cn, Wire D1, Wire D2, Wire D3, Wire D4, Wire A0, Wire A1, Wire A2, Wire A3, Wire B0,
76 Wire B1, Wire B2, Wire B3, Wire IRAMn, Wire IRAMnplus3, Wire IQn, Wire IQnplus3, Wire Y1, Wire Y2, Wire Y3, Wire Y4, Wire Feq0,
77 Wire Cnplus4, Wire OVR, Wire F3_ORAMnplus3, Wire ORAMn, Wire OQn, Wire OQnplus3)
79 Wire NSH = createWire(timeline, params);
80 Wire RSH = createWire(timeline, params);
81 Wire RAMWE = createWire(timeline, params);
82 Wire YF = createWire(timeline, params);
83 Wire LSH = createWire(timeline, params);
84 Wire QWE = createWire(timeline, params);
85 Wire notC = createWire(timeline, params);
86 Wire RAMWEandnotC = createWire(timeline, params);
87 Wire ramD1 = createWire(timeline, params);
88 Wire ramD2 = createWire(timeline, params);
89 Wire ramD3 = createWire(timeline, params);
90 Wire ramD4 = createWire(timeline, params);
91 Wire ramA1 = createWire(timeline, params);
92 Wire ramA2 = createWire(timeline, params);
93 Wire ramA3 = createWire(timeline, params);
94 Wire ramA4 = createWire(timeline, params);
95 Wire ramB1 = createWire(timeline, params);
96 Wire ramB2 = createWire(timeline, params);
97 Wire ramB3 = createWire(timeline, params);
98 Wire ramB4 = createWire(timeline, params);
99 Wire Alatch1 = createWire(timeline, params);
100 Wire Alatch2 = createWire(timeline, params);
101 Wire Alatch3 = createWire(timeline, params);
102 Wire Alatch4 = createWire(timeline, params);
103 Wire Blatch1 = createWire(timeline, params);
104 Wire Blatch2 = createWire(timeline, params);
105 Wire Blatch3 = createWire(timeline, params);
106 Wire Blatch4 = createWire(timeline, params);
108 Wire F1 = createWire(timeline, params);
109 Wire F2 = createWire(timeline, params);
110 Wire F3_inner = F3_ORAMnplus3;
111 Wire Fneq0 = createWire(timeline, params);
113 Wire Q2 = createWire(timeline, params);
114 Wire Q3 = createWire(timeline, params);
116 Wire qregD1 = createWire(timeline, params);
117 Wire qregD2 = createWire(timeline, params);
118 Wire qregD3 = createWire(timeline, params);
119 Wire qregD4 = createWire(timeline, params);
121 createAm2901DestDecode(timeline, params, I8, I7, I6, NSH, RSH, RAMWE, YF, LSH, QWE);
122 createSel3_4(timeline, params, LSH, NSH, RSH, IRAMn, F0, F1, F2, F0, F1, F2, F3_inner, F1, F2, F3_inner, IRAMnplus3, ramD1, ramD2,
124 createNand(timeline, params, C, C, notC);
125 createAnd(timeline, params, RAMWE, notC, RAMWEandnotC);
126 createRam4(timeline, params, A0, A1, A2, A3, B0, B1, B2, B3, RAMWEandnotC, ramD1, ramD2, ramD3, ramD4, ramA1, ramA2, ramA3, ramA4,
127 ramB1, ramB2, ramB3, ramB4);
128 createDlatch4(timeline, params, C, ramA1, ramA2, ramA3, ramA4, Alatch1, Alatch2, Alatch3, Alatch4);
129 createDlatch4(timeline, params, C, ramB1, ramB2, ramB3, ramB4, Blatch1, Blatch2, Blatch3, Blatch4);
130 createSel3_4(timeline, params, LSH, NSH, RSH, IQn, Q1, Q2, Q3, F0, F1, F2, F3_inner, Q2, Q3, Q4, IQnplus3, qregD1, qregD2, qregD3,
132 createAm2901QReg(timeline, params, C, QWE, qregD1, qregD2, qregD3, qregD4, Q1, Q2, Q3, Q4);
133 createAm2901ALUInclSourceDecodeInclFunctionDecode(timeline, params, I5, I4, I3, I2, I1, I0, Cn, D1, D2, D3, D4, Alatch1, Alatch2,
134 Alatch3, Alatch4, Blatch1, Blatch2, Blatch3, Blatch4, Q1, Q2, Q3, Q4, F0, F1, F2, F3_inner, Cnplus4, OVR);
135 createMux1_4(timeline, params, YF, Alatch1, Alatch2, Alatch3, Alatch4, F0, F1, F2, F3_inner, Y1, Y2, Y3, Y4);
136 createOr4(timeline, params, F0, F1, F2, F3_inner, Fneq0);
137 createNand(timeline, params, Fneq0, Fneq0, Feq0);
140 private static void createAm2901ALUFuncDecode(Timeline timeline, LogicModelParameters params, Wire I5_FN, Wire I4_SN, Wire I3_RN,
141 Wire CinE, Wire L, Wire SBE)
144 Wire notI4 = createWire(timeline, params);
145 Wire w1 = createWire(timeline, params);
146 Wire w2 = createWire(timeline, params);
147 Wire w3 = createWire(timeline, params);
149 createNand(timeline, params, I5_FN, I5_FN, notI5);
150 createNand(timeline, params, I4_SN, I4_SN, notI4);
151 createNand3(timeline, params, I4_SN, I3_RN, notI5, w1);
152 createNand(timeline, params, I5_FN, notI4, w2);
153 createNand(timeline, params, I3_RN, I4_SN, w3);
154 createNand(timeline, params, w1, w2, L);
155 createAnd(timeline, params, w3, notI5, SBE);
158 private static void createAm2901ALUInclDecode(Timeline timeline, LogicModelParameters params, Wire I5, Wire I4, Wire I3, Wire Cn,
159 Wire R1, Wire R2, Wire R3, Wire R4, Wire S1, Wire S2, Wire S3, Wire S4, Wire F1, Wire F2, Wire F3, Wire F4, Wire Cnplus4,
162 Wire CinE = createWire(timeline, params);
163 Wire L = createWire(timeline, params);
165 Wire SBE = createWire(timeline, params);
168 Wire Cnplus1 = createWire(timeline, params);
169 Wire Cnplus2 = createWire(timeline, params);
170 Wire Cnplus3 = createWire(timeline, params);
171 Wire Cnplus4_inner = Cnplus4;
173 createAm2901ALUFuncDecode(timeline, params, I5, I4, I3, CinE, L, SBE);
174 createAm2901ALUOneBit(timeline, params, Cn, CinE, R1, RN, S1, SN, SBE, FN, L, Cnplus1, F1);
175 createAm2901ALUOneBit(timeline, params, Cnplus1, CinE, R2, RN, S2, SN, SBE, FN, L, Cnplus2, F2);
176 createAm2901ALUOneBit(timeline, params, Cnplus2, CinE, R3, RN, S3, SN, SBE, FN, L, Cnplus3, F3);
177 createAm2901ALUOneBit(timeline, params, Cnplus3, CinE, R4, RN, S4, SN, SBE, FN, L, Cnplus4_inner, F4);
178 createXor(timeline, params, Cnplus3, Cnplus4_inner, OVR);
181 private static void createAm2901ALUInclSourceDecodeInclFunctionDecode(Timeline timeline, LogicModelParameters params, Wire I5, Wire I4,
182 Wire I3, Wire I2, Wire I1, Wire I0, Wire Cn, Wire D1, Wire D2, Wire D3, Wire D4, Wire A1, Wire A2, Wire A3, Wire A4, Wire B1,
183 Wire B2, Wire B3, Wire B4, Wire Q1, Wire Q2, Wire Q3, Wire Q4, Wire F1, Wire F2, Wire F3, Wire F4, Wire Cnplus4, Wire OVR)
185 Wire SQ = createWire(timeline, params);
186 Wire RA = createWire(timeline, params);
187 Wire SB = createWire(timeline, params);
188 Wire SA = createWire(timeline, params);
189 Wire RD = createWire(timeline, params);
190 Wire R1 = createWire(timeline, params);
191 Wire R2 = createWire(timeline, params);
192 Wire R3 = createWire(timeline, params);
193 Wire R4 = createWire(timeline, params);
194 Wire S1 = createWire(timeline, params);
195 Wire S2 = createWire(timeline, params);
196 Wire S3 = createWire(timeline, params);
197 Wire S4 = createWire(timeline, params);
199 createAm2901SourceDecode(timeline, params, I2, I1, I0, SQ, RA, SB, SA, RD);
200 createSel2_4(timeline, params, RD, RA, D1, D2, D3, D4, A1, A2, A3, A4, R1, R2, R3, R4);
201 createSel3_4(timeline, params, SA, SB, SQ, A1, A2, A3, A4, B1, B2, B3, B4, Q1, Q2, Q3, Q4, S1, S2, S3, S4);
202 createAm2901ALUInclDecode(timeline, params, I5, I4, I3, Cn, R1, R2, R3, R4, S1, S2, S3, S4, F1, F2, F3, F4, Cnplus4, OVR);
205 private static void createAm2901ALUOneBit(Timeline timeline, LogicModelParameters params, Wire Cin, Wire CinE, Wire R, Wire RN, Wire S,
206 Wire SN, Wire CoutE, Wire FN, Wire L, Wire Cout, Wire F)
208 Wire Cintemp = createWire(timeline, params);
209 Wire Rtemp = createWire(timeline, params);
210 Wire Stemp = createWire(timeline, params);
211 Wire xor = createWire(timeline, params);
212 Wire nand = createWire(timeline, params);
213 Wire Couttemp = createWire(timeline, params);
214 Wire Ftemp = createWire(timeline, params);
216 createAnd(timeline, params, Cin, CinE, Cintemp);
217 createXor(timeline, params, R, RN, Rtemp);
218 createXor(timeline, params, S, SN, Stemp);
219 createFulladder(timeline, params, Cintemp, Rtemp, Stemp, xor, Couttemp);
220 createNand(timeline, params, Rtemp, Stemp, nand);
221 createAnd(timeline, params, CoutE, Couttemp, Cout);
222 createMux1(timeline, params, L, xor, nand, Ftemp);
223 createXor(timeline, params, Ftemp, FN, F);
226 private static void createAm2901DestDecode(Timeline timeline, LogicModelParameters params, Wire I8, Wire I7, Wire I6, Wire NSH,
227 Wire RSH, Wire RAMWE, Wire YF, Wire LSH, Wire QWE)
230 Wire notI7 = createWire(timeline, params);
231 Wire notI6 = createWire(timeline, params);
232 Wire I8nandI7 = createWire(timeline, params);
233 Wire w1 = createWire(timeline, params);
234 Wire w2 = createWire(timeline, params);
235 Wire w3 = createWire(timeline, params);
236 Wire w4 = createWire(timeline, params);
238 createNand(timeline, params, I8, I8, notI8);
239 createNand(timeline, params, I7, I7, notI7);
240 createNand(timeline, params, I6, I6, notI6);
241 createNand(timeline, params, I8, I7, I8nandI7);
242 createNand(timeline, params, I8, notI7, w1);
243 createNand(timeline, params, notI8, notI7, RAMWE);
244 createNand(timeline, params, notI8, I7, w2);
245 createNand(timeline, params, I8nandI7, I8nandI7, LSH);
246 createNand(timeline, params, w1, w1, RSH);
247 createNand(timeline, params, w2, w2, w3);
248 createNand(timeline, params, w2, notI6, w4);
249 createNand(timeline, params, w3, notI6, YF);
250 createNand(timeline, params, w4, w4, QWE);
253 private static void createAm2901QReg(Timeline timeline, LogicModelParameters params, Wire C, Wire WE, Wire D1, Wire D2, Wire D3,
254 Wire D4, Wire Q1, Wire Q2, Wire Q3, Wire Q4)
256 Wire CandWE = createWire(timeline, params);
257 Wire nc1 = createWire(timeline, params);
258 Wire nc2 = createWire(timeline, params);
259 Wire nc3 = createWire(timeline, params);
260 Wire nc4 = createWire(timeline, params);
262 createAnd(timeline, params, C, WE, CandWE);
263 createDff(timeline, params, CandWE, D1, Q1, nc1);
264 createDff(timeline, params, CandWE, D2, Q2, nc2);
265 createDff(timeline, params, CandWE, D3, Q3, nc3);
266 createDff(timeline, params, CandWE, D4, Q4, nc4);
269 private static void createAm2901SourceDecode(Timeline timeline, LogicModelParameters params, Wire I2, Wire I1, Wire I0, Wire SQ,
270 Wire RA, Wire SB, Wire SA, Wire RD)
272 Wire notI2 = createWire(timeline, params);
273 Wire notI1 = createWire(timeline, params);
274 Wire notI0 = createWire(timeline, params);
275 Wire w1 = createWire(timeline, params);
276 Wire w2 = createWire(timeline, params);
277 Wire w3 = createWire(timeline, params);
278 Wire w4 = createWire(timeline, params);
279 Wire w5 = createWire(timeline, params);
280 Wire w6 = createWire(timeline, params);
281 Wire w7 = createWire(timeline, params);
283 createNand(timeline, params, I2, I2, notI2);
284 createNand(timeline, params, I1, I1, notI1);
285 createNand(timeline, params, I0, I0, notI0);
286 createNand(timeline, params, I2, notI1, w1);
287 createNand(timeline, params, notI2, notI1, w2);
288 createNand(timeline, params, notI2, I0, w3);
289 createNand(timeline, params, notI1, I2, w4);
290 createNand(timeline, params, notI1, notI0, w5);
291 createNand(timeline, params, notI0, w1, w6);
292 createNand(timeline, params, w2, w2, RA);
293 createNand(timeline, params, w3, w3, SB);
294 createNand(timeline, params, w4, w4, SA);
295 createNand(timeline, params, w5, I2, w7);
296 createNand(timeline, params, w6, w6, SQ);
297 createNand(timeline, params, w7, w7, RD);
300 private static void createAnd(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire Y)
302 Wire AnandB = createWire(timeline, params);
304 createNand(timeline, params, A, B, AnandB);
305 createNand(timeline, params, AnandB, AnandB, Y);
308 private static void createAnd41(Timeline timeline, LogicModelParameters params, Wire A1, Wire A2, Wire A3, Wire A4, Wire B, Wire Y1,
309 Wire Y2, Wire Y3, Wire Y4)
311 createAnd(timeline, params, A1, B, Y1);
312 createAnd(timeline, params, A2, B, Y2);
313 createAnd(timeline, params, A3, B, Y3);
314 createAnd(timeline, params, A4, B, Y4);
317 private static void createAndor414(Timeline timeline, LogicModelParameters params, Wire C1, Wire C2, Wire C3, Wire C4, Wire A1, Wire A2,
318 Wire A3, Wire A4, Wire B, Wire Y1, Wire Y2, Wire Y3, Wire Y4)
320 Wire A1andB = createWire(timeline, params);
321 Wire A2andB = createWire(timeline, params);
322 Wire A3andB = createWire(timeline, params);
323 Wire A4andB = createWire(timeline, params);
325 createAnd41(timeline, params, A1, A2, A3, A4, B, A1andB, A2andB, A3andB, A4andB);
326 createOr_4(timeline, params, C1, C2, C3, C4, A1andB, A2andB, A3andB, A4andB, Y1, Y2, Y3, Y4);
329 private static void createDemux2(Timeline timeline, LogicModelParameters params, Wire S0, Wire S1, Wire Y00, Wire Y01, Wire Y10,
332 Wire notS0 = createWire(timeline, params);
333 Wire notS1 = createWire(timeline, params);
335 createNand(timeline, params, S0, S0, notS0);
336 createNand(timeline, params, S1, S1, notS1);
337 createAnd(timeline, params, notS0, notS1, Y00);
338 createAnd(timeline, params, S0, notS1, Y01);
339 createAnd(timeline, params, notS0, S1, Y10);
340 createAnd(timeline, params, S0, S1, Y11);
343 private static void createDff(Timeline timeline, LogicModelParameters params, Wire C, Wire D, Wire Q, Wire _Q)
345 Wire w1 = createWire(timeline, params);
346 Wire w2 = createWire(timeline, params);
347 Wire w3 = createWire(timeline, params);
348 Wire nc = createWire(timeline, params);
350 create_rsLatch(timeline, params, w3, C, nc, w1);
351 createNand3(timeline, params, w1, C, w3, w2);
352 createNand(timeline, params, w2, D, w3);
353 create_rsLatch(timeline, params, w1, w2, Q, _Q);
356 private static void createDlatch(Timeline timeline, LogicModelParameters params, Wire D, Wire E, Wire Q, Wire _Q)
358 Wire DnandE = createWire(timeline, params);
359 Wire w1 = createWire(timeline, params);
361 createNand(timeline, params, D, E, DnandE);
362 createNand(timeline, params, DnandE, E, w1);
363 create_rsLatch(timeline, params, DnandE, w1, Q, _Q);
366 private static void createDlatch4(Timeline timeline, LogicModelParameters params, Wire C, Wire D1, Wire D2, Wire D3, Wire D4, Wire Q1,
367 Wire Q2, Wire Q3, Wire Q4)
369 Wire nc1 = createWire(timeline, params);
370 Wire nc2 = createWire(timeline, params);
371 Wire nc3 = createWire(timeline, params);
372 Wire nc4 = createWire(timeline, params);
374 createDlatch(timeline, params, D1, C, Q1, nc1);
375 createDlatch(timeline, params, D2, C, Q2, nc2);
376 createDlatch(timeline, params, D3, C, Q3, nc3);
377 createDlatch(timeline, params, D4, C, Q4, nc4);
380 private static void createFulladder(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire C, Wire Y, Wire Z)
382 Wire BxorC = createWire(timeline, params);
383 Wire BnandC = createWire(timeline, params);
384 Wire w1 = createWire(timeline, params);
386 createHalfadder(timeline, params, B, C, BxorC, BnandC);
387 createHalfadder(timeline, params, A, BxorC, Y, w1);
388 createNand(timeline, params, w1, BnandC, Z);
391 private static void createHalfadder(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire Y, Wire _Z)
394 Wire w1 = createWire(timeline, params);
395 Wire w2 = createWire(timeline, params);
397 createNand(timeline, params, A, B, AnandB);
398 createNand(timeline, params, A, AnandB, w1);
399 createNand(timeline, params, B, AnandB, w2);
400 createNand(timeline, params, w1, w2, Y);
403 private static void createMux1(Timeline timeline, LogicModelParameters params, Wire S0, Wire I0, Wire I1, Wire Y)
405 Wire notS0 = createWire(timeline, params);
406 Wire I0temp = createWire(timeline, params);
407 Wire I1temp = createWire(timeline, params);
409 createNand(timeline, params, S0, S0, notS0);
410 createNand(timeline, params, notS0, I0, I0temp);
411 createNand(timeline, params, S0, I1, I1temp);
412 createNand(timeline, params, I0temp, I1temp, Y);
415 private static void createMux1_4(Timeline timeline, LogicModelParameters params, Wire S0, Wire I0_0, Wire I0_1, Wire I0_2, Wire I0_3,
416 Wire I1_0, Wire I1_1, Wire I1_2, Wire I1_3, Wire Y1, Wire Y2, Wire Y3, Wire Y4)
418 createMux1(timeline, params, S0, I0_0, I1_0, Y1);
419 createMux1(timeline, params, S0, I0_1, I1_1, Y2);
420 createMux1(timeline, params, S0, I0_2, I1_2, Y3);
421 createMux1(timeline, params, S0, I0_3, I1_3, Y4);
424 private static void createNand3(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire C, Wire Y)
426 Wire AnandB = createWire(timeline, params);
427 Wire AandB = createWire(timeline, params);
429 createNand(timeline, params, A, B, AnandB);
430 createNand(timeline, params, AnandB, AnandB, AandB);
431 createNand(timeline, params, AandB, C, Y);
434 private static void createNot4(Timeline timeline, LogicModelParameters params, Wire A1, Wire A2, Wire A3, Wire A4, Wire Y1, Wire Y2,
437 createNand(timeline, params, A1, A1, Y1);
438 createNand(timeline, params, A2, A2, Y2);
439 createNand(timeline, params, A3, A3, Y3);
440 createNand(timeline, params, A4, A4, Y4);
443 private static void createOr_4(Timeline timeline, LogicModelParameters params, Wire A1, Wire A2, Wire A3, Wire A4, Wire B1, Wire B2,
444 Wire B3, Wire B4, Wire Y1, Wire Y2, Wire Y3, Wire Y4)
446 Wire notA1 = createWire(timeline, params);
447 Wire notA2 = createWire(timeline, params);
448 Wire notA3 = createWire(timeline, params);
449 Wire notA4 = createWire(timeline, params);
450 Wire notB1 = createWire(timeline, params);
451 Wire notB2 = createWire(timeline, params);
452 Wire notB3 = createWire(timeline, params);
453 Wire notB4 = createWire(timeline, params);
455 createNand(timeline, params, A1, A1, notA1);
456 createNand(timeline, params, A2, A2, notA2);
457 createNand(timeline, params, A3, A3, notA3);
458 createNand(timeline, params, A4, A4, notA4);
459 createNand(timeline, params, B1, B1, notB1);
460 createNand(timeline, params, B2, B2, notB2);
461 createNand(timeline, params, B3, B3, notB3);
462 createNand(timeline, params, B4, B4, notB4);
464 createNand(timeline, params, notA1, notB1, Y1);
465 createNand(timeline, params, notA2, notB2, Y2);
466 createNand(timeline, params, notA3, notB3, Y3);
467 createNand(timeline, params, notA4, notB4, Y4);
470 private static void createOr4(Timeline timeline, LogicModelParameters params, Wire A1, Wire A2, Wire A3, Wire A4, Wire Y)
472 Wire notA1 = createWire(timeline, params);
473 Wire notA2 = createWire(timeline, params);
474 Wire notA3 = createWire(timeline, params);
475 Wire notA4 = createWire(timeline, params);
476 Wire A1orA2 = createWire(timeline, params);
477 Wire A3orA4 = createWire(timeline, params);
478 Wire A1norA2 = createWire(timeline, params);
479 Wire A3norA4 = createWire(timeline, params);
481 createNand(timeline, params, A1, A1, notA1);
482 createNand(timeline, params, A2, A2, notA2);
483 createNand(timeline, params, A3, A3, notA3);
484 createNand(timeline, params, A4, A4, notA4);
485 createNand(timeline, params, notA1, notA2, A1orA2);
486 createNand(timeline, params, notA3, notA4, A3orA4);
487 createNand(timeline, params, A1orA2, A1orA2, A1norA2);
488 createNand(timeline, params, A3orA4, A3orA4, A3norA4);
489 createNand(timeline, params, A1norA2, A3norA4, Y);
492 private static void createRam2(Timeline timeline, LogicModelParameters params, Wire A0, Wire A1, Wire B0, Wire B1, Wire WE, Wire D1,
493 Wire D2, Wire D3, Wire D4, Wire QA1, Wire QA2, Wire QA3, Wire QA4, Wire QB1, Wire QB2, Wire QB3, Wire QB4)
495 Wire A00 = createWire(timeline, params);
496 Wire A01 = createWire(timeline, params);
497 Wire A10 = createWire(timeline, params);
498 Wire A11 = createWire(timeline, params);
499 Wire B00 = createWire(timeline, params);
500 Wire B01 = createWire(timeline, params);
501 Wire B10 = createWire(timeline, params);
502 Wire B11 = createWire(timeline, params);
503 Wire B00andWE = createWire(timeline, params);
504 Wire B01andWE = createWire(timeline, params);
505 Wire B10andWE = createWire(timeline, params);
506 Wire B11andWE = createWire(timeline, params);
507 Wire Q001 = createWire(timeline, params);
508 Wire Q002 = createWire(timeline, params);
509 Wire Q003 = createWire(timeline, params);
510 Wire Q004 = createWire(timeline, params);
511 Wire Q011 = createWire(timeline, params);
512 Wire Q012 = createWire(timeline, params);
513 Wire Q013 = createWire(timeline, params);
514 Wire Q014 = createWire(timeline, params);
515 Wire Q101 = createWire(timeline, params);
516 Wire Q102 = createWire(timeline, params);
517 Wire Q103 = createWire(timeline, params);
518 Wire Q104 = createWire(timeline, params);
519 Wire Q111 = createWire(timeline, params);
520 Wire Q112 = createWire(timeline, params);
521 Wire Q113 = createWire(timeline, params);
522 Wire Q114 = createWire(timeline, params);
523 Wire QAtempto001 = createWire(timeline, params);
524 Wire QAtempto002 = createWire(timeline, params);
525 Wire QAtempto003 = createWire(timeline, params);
526 Wire QAtempto004 = createWire(timeline, params);
527 Wire QAtempto011 = createWire(timeline, params);
528 Wire QAtempto012 = createWire(timeline, params);
529 Wire QAtempto013 = createWire(timeline, params);
530 Wire QAtempto014 = createWire(timeline, params);
531 Wire QAtempto101 = createWire(timeline, params);
532 Wire QAtempto102 = createWire(timeline, params);
533 Wire QAtempto103 = createWire(timeline, params);
534 Wire QAtempto104 = createWire(timeline, params);
535 Wire QBtempto001 = createWire(timeline, params);
536 Wire QBtempto002 = createWire(timeline, params);
537 Wire QBtempto003 = createWire(timeline, params);
538 Wire QBtempto004 = createWire(timeline, params);
539 Wire QBtempto011 = createWire(timeline, params);
540 Wire QBtempto012 = createWire(timeline, params);
541 Wire QBtempto013 = createWire(timeline, params);
542 Wire QBtempto014 = createWire(timeline, params);
543 Wire QBtempto101 = createWire(timeline, params);
544 Wire QBtempto102 = createWire(timeline, params);
545 Wire QBtempto103 = createWire(timeline, params);
546 Wire QBtempto104 = createWire(timeline, params);
548 createDemux2(timeline, params, A0, A1, A00, A01, A10, A11);
549 createDemux2(timeline, params, B0, B1, B00, B01, B10, B11);
550 createAnd41(timeline, params, B00, B01, B10, B11, WE, B00andWE, B01andWE, B10andWE, B11andWE);
551 createDlatch4(timeline, params, B00andWE, D1, D2, D3, D4, Q001, Q011, Q101, Q111);
552 createDlatch4(timeline, params, B01andWE, D1, D2, D3, D4, Q002, Q012, Q102, Q112);
553 createDlatch4(timeline, params, B10andWE, D1, D2, D3, D4, Q003, Q013, Q103, Q113);
554 createDlatch4(timeline, params, B11andWE, D1, D2, D3, D4, Q004, Q014, Q104, Q114);
555 createAnd41(timeline, params, Q001, Q002, Q003, Q004, A00, QAtempto001, QAtempto002, QAtempto003, QAtempto004);
556 createAndor414(timeline, params, QAtempto001, QAtempto002, QAtempto003, QAtempto004, Q011, Q012, Q013, Q014, A01, QAtempto011,
557 QAtempto012, QAtempto013, QAtempto014);
558 createAndor414(timeline, params, QAtempto011, QAtempto012, QAtempto013, QAtempto014, Q101, Q102, Q103, Q104, A10, QAtempto101,
559 QAtempto102, QAtempto103, QAtempto104);
560 createAndor414(timeline, params, QAtempto101, QAtempto102, QAtempto103, QAtempto104, Q111, Q112, Q113, Q114, A11, QA1, QA2, QA3,
562 createAnd41(timeline, params, Q001, Q002, Q003, Q004, B00, QBtempto001, QBtempto002, QBtempto003, QBtempto004);
563 createAndor414(timeline, params, QBtempto001, QBtempto002, QBtempto003, QBtempto004, Q011, Q012, Q013, Q014, B01, QBtempto011,
564 QBtempto012, QBtempto013, QBtempto014);
565 createAndor414(timeline, params, QBtempto011, QBtempto012, QBtempto013, QBtempto014, Q101, Q102, Q103, Q104, B10, QBtempto101,
566 QBtempto102, QBtempto103, QBtempto104);
567 createAndor414(timeline, params, QBtempto101, QBtempto102, QBtempto103, QBtempto104, Q111, Q112, Q113, Q114, B11, QB1, QB2, QB3,
571 private static void createRam4(Timeline timeline, LogicModelParameters params, Wire A0, Wire A1, Wire A2, Wire A3, Wire B0, Wire B1,
572 Wire B2, Wire B3, Wire WE, Wire D1, Wire D2, Wire D3, Wire D4, Wire QA1, Wire QA2, Wire QA3, Wire QA4, Wire QB1, Wire QB2,
575 Wire A00 = createWire(timeline, params);
576 Wire A01 = createWire(timeline, params);
577 Wire A10 = createWire(timeline, params);
578 Wire A11 = createWire(timeline, params);
579 Wire B00 = createWire(timeline, params);
580 Wire B01 = createWire(timeline, params);
581 Wire B10 = createWire(timeline, params);
582 Wire B11 = createWire(timeline, params);
583 Wire B00andWE = createWire(timeline, params);
584 Wire B01andWE = createWire(timeline, params);
585 Wire B10andWE = createWire(timeline, params);
586 Wire B11andWE = createWire(timeline, params);
587 Wire QA001 = createWire(timeline, params);
588 Wire QA002 = createWire(timeline, params);
589 Wire QA003 = createWire(timeline, params);
590 Wire QA004 = createWire(timeline, params);
591 Wire QA011 = createWire(timeline, params);
592 Wire QA012 = createWire(timeline, params);
593 Wire QA013 = createWire(timeline, params);
594 Wire QA014 = createWire(timeline, params);
595 Wire QA101 = createWire(timeline, params);
596 Wire QA102 = createWire(timeline, params);
597 Wire QA103 = createWire(timeline, params);
598 Wire QA104 = createWire(timeline, params);
599 Wire QA111 = createWire(timeline, params);
600 Wire QA112 = createWire(timeline, params);
601 Wire QA113 = createWire(timeline, params);
602 Wire QA114 = createWire(timeline, params);
603 Wire QB001 = createWire(timeline, params);
604 Wire QB002 = createWire(timeline, params);
605 Wire QB003 = createWire(timeline, params);
606 Wire QB004 = createWire(timeline, params);
607 Wire QB011 = createWire(timeline, params);
608 Wire QB012 = createWire(timeline, params);
609 Wire QB013 = createWire(timeline, params);
610 Wire QB014 = createWire(timeline, params);
611 Wire QB101 = createWire(timeline, params);
612 Wire QB102 = createWire(timeline, params);
613 Wire QB103 = createWire(timeline, params);
614 Wire QB104 = createWire(timeline, params);
615 Wire QB111 = createWire(timeline, params);
616 Wire QB112 = createWire(timeline, params);
617 Wire QB113 = createWire(timeline, params);
618 Wire QB114 = createWire(timeline, params);
619 Wire QAtempto001 = createWire(timeline, params);
620 Wire QAtempto002 = createWire(timeline, params);
621 Wire QAtempto003 = createWire(timeline, params);
622 Wire QAtempto004 = createWire(timeline, params);
623 Wire QAtempto011 = createWire(timeline, params);
624 Wire QAtempto012 = createWire(timeline, params);
625 Wire QAtempto013 = createWire(timeline, params);
626 Wire QAtempto014 = createWire(timeline, params);
627 Wire QAtempto101 = createWire(timeline, params);
628 Wire QAtempto102 = createWire(timeline, params);
629 Wire QAtempto103 = createWire(timeline, params);
630 Wire QAtempto104 = createWire(timeline, params);
631 Wire QBtempto001 = createWire(timeline, params);
632 Wire QBtempto002 = createWire(timeline, params);
633 Wire QBtempto003 = createWire(timeline, params);
634 Wire QBtempto004 = createWire(timeline, params);
635 Wire QBtempto011 = createWire(timeline, params);
636 Wire QBtempto012 = createWire(timeline, params);
637 Wire QBtempto013 = createWire(timeline, params);
638 Wire QBtempto014 = createWire(timeline, params);
639 Wire QBtempto101 = createWire(timeline, params);
640 Wire QBtempto102 = createWire(timeline, params);
641 Wire QBtempto103 = createWire(timeline, params);
642 Wire QBtempto104 = createWire(timeline, params);
644 createDemux2(timeline, params, A0, A1, A00, A01, A10, A11);
645 createDemux2(timeline, params, B0, B1, B00, B01, B10, B11);
646 createAnd41(timeline, params, B00, B01, B10, B11, WE, B00andWE, B01andWE, B10andWE, B11andWE);
647 createRam2(timeline, params, A2, A3, B2, B3, B00andWE, D1, D2, D3, D4, QA001, QA011, QA101, QA111, QB001, QB011, QB101, QB111);
648 createRam2(timeline, params, A2, A3, B2, B3, B01andWE, D1, D2, D3, D4, QA002, QA012, QA102, QA112, QB002, QB012, QB102, QB112);
649 createRam2(timeline, params, A2, A3, B2, B3, B10andWE, D1, D2, D3, D4, QA003, QA013, QA103, QA113, QB003, QB013, QB103, QB113);
650 createRam2(timeline, params, A2, A3, B2, B3, B11andWE, D1, D2, D3, D4, QA004, QA014, QA104, QA114, QB004, QB014, QB104, QB114);
651 createAnd41(timeline, params, QA001, QA002, QA003, QA004, A00, QAtempto001, QAtempto002, QAtempto003, QAtempto004);
652 createAndor414(timeline, params, QAtempto001, QAtempto002, QAtempto003, QAtempto004, QA011, QA012, QA013, QA014, A01, QAtempto011,
653 QAtempto012, QAtempto013, QAtempto014);
654 createAndor414(timeline, params, QAtempto011, QAtempto012, QAtempto013, QAtempto014, QA101, QA102, QA103, QA104, A10, QAtempto101,
655 QAtempto102, QAtempto103, QAtempto104);
656 createAndor414(timeline, params, QAtempto101, QAtempto102, QAtempto103, QAtempto104, QA111, QA112, QA113, QA114, A11, QA1, QA2, QA3,
658 createAnd41(timeline, params, QB001, QB002, QB003, QB004, B00, QBtempto001, QBtempto002, QBtempto003, QBtempto004);
659 createAndor414(timeline, params, QBtempto001, QBtempto002, QBtempto003, QBtempto004, QB011, QB012, QB013, QB014, B01, QBtempto011,
660 QBtempto012, QBtempto013, QBtempto014);
661 createAndor414(timeline, params, QBtempto011, QBtempto012, QBtempto013, QBtempto014, QB101, QB102, QB103, QB104, B10, QBtempto101,
662 QBtempto102, QBtempto103, QBtempto104);
663 createAndor414(timeline, params, QBtempto101, QBtempto102, QBtempto103, QBtempto104, QB111, QB112, QB113, QB114, B11, QB1, QB2, QB3,
667 private static void createSel2_4(Timeline timeline, LogicModelParameters params, Wire SA, Wire SB, Wire A1, Wire A2, Wire A3, Wire A4,
668 Wire B1, Wire B2, Wire B3, Wire B4, Wire Y1, Wire Y2, Wire Y3, Wire Y4)
670 Wire A1temp = createWire(timeline, params);
671 Wire A2temp = createWire(timeline, params);
672 Wire A3temp = createWire(timeline, params);
673 Wire A4temp = createWire(timeline, params);
674 Wire B1temp = createWire(timeline, params);
675 Wire B2temp = createWire(timeline, params);
676 Wire B3temp = createWire(timeline, params);
677 Wire B4temp = createWire(timeline, params);
679 createNand(timeline, params, A1, SA, A1temp);
680 createNand(timeline, params, A2, SA, A2temp);
681 createNand(timeline, params, A3, SA, A3temp);
682 createNand(timeline, params, A4, SA, A4temp);
683 createNand(timeline, params, B1, SB, B1temp);
684 createNand(timeline, params, B2, SB, B2temp);
685 createNand(timeline, params, B3, SB, B3temp);
686 createNand(timeline, params, B4, SB, B4temp);
687 createNand(timeline, params, A1temp, B1temp, Y1);
688 createNand(timeline, params, A2temp, B2temp, Y2);
689 createNand(timeline, params, A3temp, B3temp, Y3);
690 createNand(timeline, params, A4temp, B4temp, Y4);
693 private static void createSel3_4(Timeline timeline, LogicModelParameters params, Wire SA, Wire SB, Wire SC, Wire A1, Wire A2, Wire A3,
694 Wire A4, Wire B1, Wire B2, Wire B3, Wire B4, Wire C1, Wire C2, Wire C3, Wire C4, Wire Y1, Wire Y2, Wire Y3, Wire Y4)
696 Wire selAB1 = createWire(timeline, params);
697 Wire selAB2 = createWire(timeline, params);
698 Wire selAB3 = createWire(timeline, params);
699 Wire selAB4 = createWire(timeline, params);
700 Wire notSelAB1 = createWire(timeline, params);
701 Wire notSelAB2 = createWire(timeline, params);
702 Wire notSelAB3 = createWire(timeline, params);
703 Wire notSelAB4 = createWire(timeline, params);
704 Wire C1temp = createWire(timeline, params);
705 Wire C2temp = createWire(timeline, params);
706 Wire C3temp = createWire(timeline, params);
707 Wire C4temp = createWire(timeline, params);
709 createSel2_4(timeline, params, SA, SB, A1, A2, A3, A4, B1, B2, B3, B4, selAB1, selAB2, selAB3, selAB4);
710 createNot4(timeline, params, selAB1, selAB2, selAB3, selAB4, notSelAB1, notSelAB2, notSelAB3, notSelAB4);
711 createNand(timeline, params, C1, SC, C1temp);
712 createNand(timeline, params, C2, SC, C2temp);
713 createNand(timeline, params, C3, SC, C3temp);
714 createNand(timeline, params, C4, SC, C4temp);
715 createNand(timeline, params, notSelAB1, C1temp, Y1);
716 createNand(timeline, params, notSelAB2, C2temp, Y2);
717 createNand(timeline, params, notSelAB3, C3temp, Y3);
718 createNand(timeline, params, notSelAB4, C4temp, Y4);
721 private static void createXor(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire Y)
723 Wire AnandB = createWire(timeline, params);
724 Wire w1 = createWire(timeline, params);
725 Wire w2 = createWire(timeline, params);
727 createNand(timeline, params, A, B, AnandB);
728 createNand(timeline, params, A, AnandB, w1);
729 createNand(timeline, params, B, AnandB, w2);
730 createNand(timeline, params, w1, w2, Y);
733 @SuppressWarnings("unused") // AndGate and NotGate
734 private static void createNand(Timeline timeline, LogicModelParameters params, Wire A, Wire B, Wire Y)
736 Wire w = new Wire(timeline, 1, params.wireTravelTime);
737 new AndGate(timeline, params.gateProcessTime, w.createReadWriteEnd(), A.createReadOnlyEnd(), B.createReadOnlyEnd());
738 // -2 because of delay 1 of wire and delay 1 of AndGate.
739 // Math.max to avoid negative / zero delays, which are forbidden by Timeline.
740 new NotGate(timeline, Math.max(1, params.gateProcessTime - 2), w.createReadOnlyEnd(), Y.createReadWriteEnd());
743 private static Wire createWire(Timeline timeline, LogicModelParameters params)
745 return new Wire(timeline, 1, params.wireTravelTime);