net.mograsim.machine/src/net/mograsim/machine/standard/memory/WordAddressableMemoryComponent.java

   1 package net.mograsim.machine.standard.memory;
   2
   3 import java.util.List;
   4
   5 import net.mograsim.logic.core.components.BasicComponent;
   6 import net.mograsim.logic.core.timeline.Timeline;
   7 import net.mograsim.logic.core.types.Bit;
   8 import net.mograsim.logic.core.types.BitVector;
   9 import net.mograsim.logic.core.wires.Wire.ReadEnd;
  10 import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
  11 import net.mograsim.machine.MainMemoryDefinition;
  12
  13 /**
  14  * A memory component that only allows access to words of a specific length
  15  */
  16 public class WordAddressableMemoryComponent extends BasicComponent
  17 {
  18         private final WordAddressableMemory memory;
  19         private final static Bit read = Bit.ONE;
  20
  21         private ReadWriteEnd data;
  22         private ReadEnd rWBit, address;
  23
  24         /**
  25          * @param data    The bits of this ReadEnd are the value that is written to/read from memory; The bit width of this wire is the width of
  26          *                a memory word
  27          * @param rWBit   The value of the 0th bit dictates the mode: 0: Write, 1: Read
  28          * @param address The bits of this ReadEnd address the memory cell to read/write
  29          */
  30         public WordAddressableMemoryComponent(Timeline timeline, int processTime, MainMemoryDefinition definition, ReadWriteEnd data,
  31                         ReadEnd rWBit, ReadEnd address)
  32         {
  33                 super(timeline, processTime);
  34                 if(data.length() != definition.getCellWidth())
  35                         throw new IllegalArgumentException(String.format("Bit width of data wire does not match main memory definition. Expected: %d Actual: %d", definition.getCellWidth(), data.length()));
  36                 if(rWBit.length() != 1)
  37                         throw new IllegalArgumentException(String.format("Bit width of read/write mode select wire is unexpected. Expected: 1 Actual: %d", rWBit.length()));
  38                 if(address.length() != definition.getMemoryAddressBits())
  39                         throw new IllegalArgumentException(String.format("Bit width of address wire does not match main memory definition. Expected: %d Actual: %d", definition.getMemoryAddressBits(), address.length()));
  40                 this.data = data;
  41                 this.rWBit = rWBit;
  42                 this.address = address;
  43                 data.registerObserver(this);
  44                 rWBit.registerObserver(this);
  45                 address.registerObserver(this);
  46
  47                 memory = new WordAddressableMemory(definition);
  48         }
  49
  50         @Override
  51         protected void compute()
  52         {
  53                 if (!address.hasNumericValue())
  54                 {
  55                         if (read.equals(rWBit.getValue()))
  56                                 data.feedSignals(BitVector.of(Bit.U, data.length()));
  57                         else
  58                                 data.clearSignals();
  59                         return;
  60                 }
  61                 long addressed = address.getUnsignedValue();
  62                 if (read.equals(rWBit.getValue()))
  63                         data.feedSignals(memory.getCell(addressed));
  64                 else
  65                 {
  66                         data.clearSignals();
  67                         memory.setCell(addressed, data.getValues());
  68                 }
  69         }
  70
  71         @Override
  72         public List<ReadEnd> getAllInputs()
  73         {
  74                 return List.of(data, rWBit, address);
  75         }
  76
  77         @Override
  78         public List<ReadWriteEnd> getAllOutputs()
  79         {
  80                 return List.of(data);
  81         }
  82 }