1 package net.mograsim.logic.core.components.gates;
3 import net.mograsim.logic.core.timeline.Timeline;
4 import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
5 import net.mograsim.logic.core.wires.CoreWire.ReadEnd;
6 import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
9 * Outputs 1 when the number of 1 inputs is odd.
11 * @author Fabian Stemmler
13 public class CoreXorGate extends MultiInputCoreGate
15 public CoreXorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)
17 super(timeline, processTime, BitVectorMutator::xor, out, in);