plugins/net.mograsim.logic.model.verilog/src/net/mograsim/logic/model/verilog/converter/components/TriStateBufferConverter.java

   1 package net.mograsim.logic.model.verilog.converter.components;
   2
   3 import java.util.ArrayList;
   4 import java.util.List;
   5
   6 import com.google.gson.JsonElement;
   7
   8 import net.mograsim.logic.core.types.Bit;
   9 import net.mograsim.logic.core.types.BitVector;
  10 import net.mograsim.logic.model.model.components.atomic.ModelTriStateBuffer;
  11 import net.mograsim.logic.model.model.wires.Pin;
  12 import net.mograsim.logic.model.verilog.converter.ComponentConversionResult;
  13 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogComponentDeclarationMapping;
  14 import net.mograsim.logic.model.verilog.converter.ModelComponentToVerilogConverter;
  15 import net.mograsim.logic.model.verilog.converter.PinNameBit;
  16 import net.mograsim.logic.model.verilog.model.VerilogComponentDeclaration;
  17 import net.mograsim.logic.model.verilog.model.VerilogComponentImplementation;
  18 import net.mograsim.logic.model.verilog.model.expressions.Constant;
  19 import net.mograsim.logic.model.verilog.model.expressions.Expression;
  20 import net.mograsim.logic.model.verilog.model.expressions.SignalReference;
  21 import net.mograsim.logic.model.verilog.model.signals.IOPort;
  22 import net.mograsim.logic.model.verilog.model.signals.Input;
  23 import net.mograsim.logic.model.verilog.model.signals.Output;
  24 import net.mograsim.logic.model.verilog.model.signals.Wire;
  25 import net.mograsim.logic.model.verilog.model.statements.Assign;
  26 import net.mograsim.logic.model.verilog.model.statements.ComponentReference;
  27 import net.mograsim.logic.model.verilog.model.statements.Statement;
  28 import net.mograsim.logic.model.verilog.model.statements.WireDeclaration;
  29 import net.mograsim.logic.model.verilog.utils.IdentifierGenerator;
  30 import net.mograsim.logic.model.verilog.utils.UnionFind;
  31
  32 public class TriStateBufferConverter implements ComponentConverter<ModelTriStateBuffer>
  33 {
  34         // TODO don't hardcode this
  35         private static final VerilogComponentDeclaration TSBW_COMBINE = new VerilogComponentDeclaration("tsbw_combine",
  36                         List.of(new Input("wA", 2), new Input("wB", 2), new Output("res", 2)));
  37         private static final VerilogComponentDeclaration TSBW_CONDITIONAL = new VerilogComponentDeclaration("tsbw_conditional",
  38                         List.of(new Input("cond", 2), new Input("onTrue", 2), new Input("onFalse", 2), new Output("res", 2)));
  39
  40         @Override
  41         public ComponentConversionResult convert(ModelTriStateBuffer modelComponent, String modelID, JsonElement params, String verilogID)
  42         {
  43                 UnionFind<PinNameBit> connectedPins = new UnionFind<>();
  44                 ModelComponentToVerilogComponentDeclarationMapping mapping = ModelComponentToVerilogConverter
  45                                 .generateCanonicalDeclarationMapping(modelComponent, connectedPins, modelID, params, verilogID);
  46                 VerilogComponentDeclaration declaration = mapping.getVerilogComponentDeclaration();
  47
  48                 List<Statement> statements = new ArrayList<>();
  49
  50                 PinNameBit condPinbit = new PinNameBit(modelComponent.getEnablePin().name, 0);
  51                 IOPort condPre = mapping.getPrePinMapping().get(condPinbit).getVerilogPort();
  52                 IOPort condOut = mapping.getOutPinMapping().get(condPinbit).getVerilogPort();
  53                 IOPort condRes = mapping.getResPinMapping().get(condPinbit).getVerilogPort();
  54                 Expression condrResRef = new SignalReference(condRes);
  55
  56                 statements.add(new Assign(condOut, new SignalReference(condPre)));
  57
  58                 IdentifierGenerator idGen = ModelComponentToVerilogConverter.generateIdentifierGenerator(declaration);
  59
  60                 Pin inputPin = modelComponent.getInputPin();
  61                 Pin outputPin = modelComponent.getOutputPin();
  62                 for (int bit = 0; bit < inputPin.logicWidth; bit++)
  63                 {
  64                         PinNameBit inputPinbit = new PinNameBit(inputPin.name, bit);
  65                         PinNameBit outputPinbit = new PinNameBit(outputPin.name, bit);
  66
  67                         IOPort inPre = mapping.getPrePinMapping().get(inputPinbit).getVerilogPort();
  68                         IOPort inOut = mapping.getOutPinMapping().get(inputPinbit).getVerilogPort();
  69                         IOPort inRes = mapping.getResPinMapping().get(inputPinbit).getVerilogPort();
  70                         IOPort outPre = mapping.getPrePinMapping().get(outputPinbit).getVerilogPort();
  71                         IOPort outOut = mapping.getOutPinMapping().get(outputPinbit).getVerilogPort();
  72                         Expression inPreRef = new SignalReference(inPre);
  73                         Expression inResRef = new SignalReference(inRes);
  74                         Expression outPreRef = new SignalReference(outPre);
  75                         Expression outOutRef = new SignalReference(outOut);
  76
  77                         Wire condTmp = new Wire(idGen.generateID("cond_tmp_" + bit), 2);
  78                         SignalReference condTmpRef = new SignalReference(condTmp);
  79                         statements.add(new WireDeclaration(condTmp));
  80
  81                         statements.add(new Assign(inOut, inPreRef));
  82                         statements.add(new ComponentReference(idGen.generateID("cond_" + bit), TSBW_CONDITIONAL,
  83                                         List.of(condrResRef, inResRef, new Constant(BitVector.of(Bit.ZERO, 2)), condTmpRef)));
  84                         statements
  85                                         .add(new ComponentReference(idGen.generateID("comb_" + bit), TSBW_COMBINE, List.of(outPreRef, condTmpRef, outOutRef)));
  86                 }
  87
  88                 VerilogComponentImplementation implementation = new VerilogComponentImplementation(declaration, statements);
  89
  90                 return new ComponentConversionResult(mapping, implementation);
  91         }
  92 }