1 package net.mograsim.logic.model.verilog.model.expressions;
5 import net.mograsim.logic.model.verilog.model.signals.Signal;
7 public abstract class Expression
9 private final int width;
11 public Expression(int width)
21 throw new IllegalArgumentException("Width can't be negative");
29 public abstract String toVerilogCode();
31 public abstract Set<Signal> getReferencedSignals();