1 package net.mograsim.logic.model.verilog.model.signals;
3 import java.util.Objects;
5 public abstract class Signal
7 private final Type type;
8 private final String name;
9 private final int width;
11 public Signal(Type type, String name, int width)
13 this.type = Objects.requireNonNull(type);
14 this.name = Objects.requireNonNull(name);
23 throw new IllegalArgumentException("Signal width is negative: " + width);
31 public String getName()
41 public String toReferenceVerilogCode()
47 public String toString()
49 return name + "[" + getWidth() + "]";
57 result = prime * result + ((name == null) ? 0 : name.hashCode());
58 result = prime * result + ((type == null) ? 0 : type.hashCode());
59 result = prime * result + width;
64 public boolean equals(Object obj)
70 if (getClass() != obj.getClass())
72 Signal other = (Signal) obj;
75 if (other.name != null)
77 } else if (!name.equals(other.name))
79 if (type != other.type)
81 if (width != other.width)
86 public static enum Type
88 WIRE, IO_INPUT, IO_OUTPUT;