1 package net.mograsim.logic.model.verilog.model.statements;
3 import java.util.Objects;
6 import net.mograsim.logic.model.verilog.model.expressions.Expression;
7 import net.mograsim.logic.model.verilog.model.signals.Signal;
8 import net.mograsim.logic.model.verilog.utils.CollectionsUtils;
10 public class Assign extends Statement
12 private final Signal target;
13 private final Expression source;
15 public Assign(Signal target, Expression source)
17 this.target = Objects.requireNonNull(target);
18 this.source = Objects.requireNonNull(source);
25 if (source.getWidth() != target.getWidth())
26 throw new IllegalArgumentException("Signal widthes don't match");
29 public Signal getTarget()
34 public Expression getSource()
40 public String toVerilogCode()
42 return "assign " + target.toReferenceVerilogCode() + " = " + source.toVerilogCode() + ";";
46 public Set<String> getDefinedNames()
52 public Set<Signal> getDefinedSignals()
58 public Set<Signal> getReferencedSignals()
60 return CollectionsUtils.union(Set.of(target), source.getReferencedSignals());
64 public String toString()
66 return target.getName() + " = " + source;
74 result = prime * result + ((source == null) ? 0 : source.hashCode());
75 result = prime * result + ((target == null) ? 0 : target.hashCode());
80 public boolean equals(Object obj)
86 if (getClass() != obj.getClass())
88 Assign other = (Assign) obj;
91 if (other.source != null)
93 } else if (!source.equals(other.source))
97 if (other.target != null)
99 } else if (!target.equals(other.target))