1 package net.mograsim.machine;
3 import net.mograsim.logic.core.components.CoreClock;
4 import net.mograsim.logic.core.timeline.Timeline;
5 import net.mograsim.logic.core.types.BitVector;
6 import net.mograsim.logic.model.model.LogicModel;
7 import net.mograsim.machine.mi.AssignableMicroInstructionMemory;
8 import net.mograsim.machine.standard.memory.AssignableMainMemory;
10 public interface Machine
12 MachineDefinition getDefinition();
16 LogicModel getModel();
20 BitVector getRegister(Register r);
22 void setRegister(Register r, BitVector value);
24 Timeline getTimeline();
26 AssignableMainMemory getMainMemory();
28 AssignableMicroInstructionMemory getMicroInstructionMemory();