1 package net.mograsim.logic.model.verilog.model;
3 import java.util.ArrayList;
4 import java.util.HashSet;
6 import java.util.Objects;
8 import java.util.stream.Collectors;
10 import net.mograsim.logic.model.verilog.model.Signal.Type;
12 public class VerilogComponentImplementation
14 private final VerilogComponentDeclaration declaration;
15 private final Set<Wire> internalWires;
16 private final Set<Assign> assigns;
17 private final Set<ComponentReference> subcomponents;
19 public VerilogComponentImplementation(VerilogComponentDeclaration declaration, Set<Wire> internalWires, Set<Assign> assigns,
20 Set<ComponentReference> subcomponents)
22 this.declaration = Objects.requireNonNull(declaration);
23 this.internalWires = Set.copyOf(internalWires);
24 this.assigns = Set.copyOf(assigns);
25 this.subcomponents = Set.copyOf(subcomponents);
32 Set<Signal> allSignals = new HashSet<>();
33 allSignals.addAll(declaration.getIOPorts());
34 allSignals.addAll(internalWires);
36 Set<String> usedNames = declaration.getIOPorts().stream().map(IOPort::getName).collect(Collectors.toCollection(HashSet::new));
38 for (Wire wire : internalWires)
39 if (!usedNames.add(wire.getName()))
40 throw new IllegalArgumentException("Name occurs twice: " + wire.getName());
42 for (Assign assign : assigns)
43 if (!allSignals.contains(assign.getSource()) || !allSignals.contains(assign.getTarget()))
44 throw new IllegalArgumentException("Referenced an unknown signal: " + assign.getSource());
46 for (ComponentReference subcomponent : subcomponents)
47 if (!usedNames.add(subcomponent.getName()))
48 throw new IllegalArgumentException("Name occurs twice: " + subcomponent.getName());
49 else if (!subcomponent.getArguments().stream().filter(s -> s.getType() != Type.CONSTANT).allMatch(allSignals::contains))
51 List<Signal> unknownSignals = new ArrayList<>(subcomponent.getArguments());
52 unknownSignals.removeAll(allSignals);
53 // we know this list contains at least one element
54 throw new IllegalArgumentException("Assigning a signal not in the component: " + unknownSignals.get(0));
58 public VerilogComponentDeclaration getDeclaration()
63 public Set<Wire> getInternalWires()
68 public Set<Assign> getAssigns()
73 public Set<ComponentReference> getSubcomponents()
78 public String toVerilogCode()
80 StringBuilder sb = new StringBuilder();
82 sb.append("module " + declaration.getID());
83 sb.append(declaration.getIOPorts().stream().map(IOPort::toDeclarationVerilogCode).collect(Collectors.joining(", ", "(", ")")));
86 for (Wire wire : internalWires)
87 sb.append(wire.toDeclarationVerilogCode() + "\n");
88 if (!internalWires.isEmpty())
91 for (Assign assign : assigns)
92 sb.append(assign.toVerilogCode() + "\n");
93 if (!assigns.isEmpty())
96 for (ComponentReference subcomponent : subcomponents)
97 sb.append(subcomponent.toVerilogCode() + "\n");
98 if (!subcomponents.isEmpty())
101 sb.append("endmodule\n");
103 return sb.toString();
107 public String toString()
109 return "Implementation[" + declaration.getID() + "]";
113 public int hashCode()
115 final int prime = 31;
117 result = prime * result + ((assigns == null) ? 0 : assigns.hashCode());
118 result = prime * result + ((declaration == null) ? 0 : declaration.hashCode());
119 result = prime * result + ((internalWires == null) ? 0 : internalWires.hashCode());
120 result = prime * result + ((subcomponents == null) ? 0 : subcomponents.hashCode());
125 public boolean equals(Object obj)
131 if (getClass() != obj.getClass())
133 VerilogComponentImplementation other = (VerilogComponentImplementation) obj;
136 if (other.assigns != null)
138 } else if (!assigns.equals(other.assigns))
140 if (declaration == null)
142 if (other.declaration != null)
144 } else if (!declaration.equals(other.declaration))
146 if (internalWires == null)
148 if (other.internalWires != null)
150 } else if (!internalWires.equals(other.internalWires))
152 if (subcomponents == null)
154 if (other.subcomponents != null)
156 } else if (!subcomponents.equals(other.subcomponents))