import era.mi.logic.Bit;
import era.mi.logic.Simulation;
+import era.mi.logic.components.Connector;
import era.mi.logic.components.Demux;
import era.mi.logic.components.Merger;
import era.mi.logic.components.Mux;
import era.mi.logic.wires.WireArray;
import era.mi.logic.wires.WireArray.WireArrayEnd;
+@SuppressWarnings("unused")
class ComponentTest
{
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();
enI.feedSignals(Bit.ONE);
aI.feedSignals(Bit.ONE);
+ bI.feedSignals(Bit.Z);
Simulation.TIMELINE.executeAll();
assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);
}
-// @Test
+ @Test
void wireConnections()
{
// Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde
cI.feedSignals(Bit.Z);
test.assertAfterSimulationIs(print, Bit.Z);
- new Connector(b, c);
+ new Connector(b, c).connect();
test.assertAfterSimulationIs(print, Bit.Z);
System.err.println("ONE");
bI.feedSignals(Bit.ONE);
bI.feedSignals(Bit.Z);
test.assertAfterSimulationIs(print, Bit.Z);
- new Connector(a, b);
+ new Connector(a, b).connect();
System.err.println("Z 2");
aI.feedSignals(Bit.Z);
test.assertAfterSimulationIs(print, Bit.Z);