import net.mograsim.logic.core.wires.CoreWire.ReadWriteEnd;
import net.mograsim.machine.MainMemoryDefinition;
-class WordAddressableMemoryTest {
-
+class WordAddressableMemoryTest
+{
+
private Timeline t = new Timeline(10);
@Test
CoreWire rW = new CoreWire(t, 1, 2);
CoreWire data = new CoreWire(t, 16, 2);
CoreWire address = new CoreWire(t, 64, 2);
- CoreWire clock = new CoreWire(t, 1, 2);
ReadWriteEnd rWI = rW.createReadWriteEnd();
ReadWriteEnd dataI = data.createReadWriteEnd();
ReadWriteEnd addressI = address.createReadWriteEnd();
- ReadWriteEnd clockI = clock.createReadWriteEnd();
@SuppressWarnings("unused")
- CoreWordAddressableMemory memory = new CoreWordAddressableMemory(t, 4, new WordAddressableMemory(MainMemoryDefinition.create(64, 16, 4096L, Long.MAX_VALUE)), data.createReadWriteEnd(),
- rW.createReadOnlyEnd(), address.createReadOnlyEnd(), clock.createReadOnlyEnd());
+ CoreWordAddressableMemory memory = new CoreWordAddressableMemory(t, 4,
+ new WordAddressableMemory(MainMemoryDefinition.create(64, 16, 4096L, Long.MAX_VALUE)), data.createReadWriteEnd(),
+ rW.createReadOnlyEnd(), address.createReadOnlyEnd());
- clockI.feedSignals(Bit.ONE);
-
Random r = new Random();
for (long j = 1; j > 0; j *= 2)
{