import era.mi.logic.wires.Wire;\r
import era.mi.logic.wires.Wire.ReadEnd;\r
import era.mi.logic.wires.Wire.ReadWriteEnd;\r
import era.mi.logic.wires.Wire;\r
import era.mi.logic.wires.Wire.ReadEnd;\r
import era.mi.logic.wires.Wire.ReadWriteEnd;\r
* @param select Indexes the input array which is to be mapped to the output. Must have enough bits to index all inputs.\r
* @param inputs One of these inputs is mapped to the output, depending on the select bits\r
*/\r
* @param select Indexes the input array which is to be mapped to the output. Must have enough bits to index all inputs.\r
* @param inputs One of these inputs is mapped to the output, depending on the select bits\r
*/\r
- public Mux(int processTime, ReadWriteEnd out, ReadEnd select, ReadEnd... inputs)\r
+ public Mux(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd select, ReadEnd... inputs)\r