import era.mi.logic.components.Demux;
import era.mi.logic.components.Merger;
import era.mi.logic.components.Mux;
import era.mi.logic.components.Demux;
import era.mi.logic.components.Merger;
import era.mi.logic.components.Mux;
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();
enI.feedSignals(Bit.ONE);
aI.feedSignals(Bit.ONE);
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();
enI.feedSignals(Bit.ONE);
aI.feedSignals(Bit.ONE);
test.assertAfterSimulationIs(print, Bit.Z);
System.err.println("ONE");
bI.feedSignals(Bit.ONE);
test.assertAfterSimulationIs(print, Bit.Z);
System.err.println("ONE");
bI.feedSignals(Bit.ONE);
System.err.println("Z 2");
aI.feedSignals(Bit.Z);
test.assertAfterSimulationIs(print, Bit.Z);
System.err.println("Z 2");
aI.feedSignals(Bit.Z);
test.assertAfterSimulationIs(print, Bit.Z);