import era.mi.logic.components.Demux;\r
import era.mi.logic.components.Merger;\r
import era.mi.logic.components.Mux;\r
import era.mi.logic.components.Demux;\r
import era.mi.logic.components.Merger;\r
import era.mi.logic.components.Mux;\r
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();\r
enI.feedSignals(Bit.ONE);\r
aI.feedSignals(Bit.ONE);\r
WireArrayEnd enI = en.createInput(), aI = a.createInput(), bI = b.createInput();\r
enI.feedSignals(Bit.ONE);\r
aI.feedSignals(Bit.ONE);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
System.err.println("ONE");\r
bI.feedSignals(Bit.ONE);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
System.err.println("ONE");\r
bI.feedSignals(Bit.ONE);\r
System.err.println("Z 2");\r
aI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
System.err.println("Z 2");\r
aI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r