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Merge branch 'development' of https://gitlab.lrz.de/lrr-tum/students/eragp-misim...
[Mograsim.git]
/
net.mograsim.logic.core
/
src
/
net
/
mograsim
/
logic
/
core
/
components
/
gates
/
MultiInputGate.java
diff --git
a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
index
afc8951
..
da30281
100644
(file)
--- a/
net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
+++ b/
net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/MultiInputGate.java
@@
-4,8
+4,8
@@
import java.util.List;
import net.mograsim.logic.core.components.BasicComponent;
import net.mograsim.logic.core.timeline.Timeline;
import net.mograsim.logic.core.components.BasicComponent;
import net.mograsim.logic.core.timeline.Timeline;
-import net.mograsim.logic.core.types.MutationOperation;
import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
import net.mograsim.logic.core.types.BitVector.BitVectorMutator;
+import net.mograsim.logic.core.types.MutationOperation;
import net.mograsim.logic.core.wires.Wire.ReadEnd;
import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
import net.mograsim.logic.core.wires.Wire.ReadEnd;
import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
@@
-15,6
+15,7
@@
public abstract class MultiInputGate extends BasicComponent
protected ReadWriteEnd out;
protected final int length;
protected MutationOperation op;
protected ReadWriteEnd out;
protected final int length;
protected MutationOperation op;
+ protected boolean invert = false;
protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in)
{
protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, ReadWriteEnd out, ReadEnd... in)
{
@@
-28,11
+29,17
@@
public abstract class MultiInputGate extends BasicComponent
{
if (w.length() != length)
throw new IllegalArgumentException("All wires connected to the gate must be of uniform length.");
{
if (w.length() != length)
throw new IllegalArgumentException("All wires connected to the gate must be of uniform length.");
- w.
add
Observer(this);
+ w.
register
Observer(this);
}
this.out = out;
}
}
this.out = out;
}
+ protected MultiInputGate(Timeline timeline, int processTime, MutationOperation op, boolean invert, ReadWriteEnd out, ReadEnd... in)
+ {
+ this(timeline, processTime, op, out, in);
+ this.invert = invert;
+ }
+
@Override
public List<ReadEnd> getAllInputs()
{
@Override
public List<ReadEnd> getAllInputs()
{
@@
-51,6
+58,6
@@
public abstract class MultiInputGate extends BasicComponent
BitVectorMutator mutator = BitVectorMutator.empty();
for (ReadEnd w : in)
op.apply(mutator, w.getValues());
BitVectorMutator mutator = BitVectorMutator.empty();
for (ReadEnd w : in)
op.apply(mutator, w.getValues());
- out.feedSignals(
mutator.get
());
+ out.feedSignals(
invert ? mutator.toBitVector().not() : mutator.toBitVector
());
}
}
}
}