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Merged LD and _RLD inputs of ModelAm2910RegCntr into one pin
[Mograsim.git]
/
plugins
/
net.mograsim.logic.model.am2900
/
components
/
net
/
mograsim
/
logic
/
model
/
am2900
/
components
/
am2910
/
Am2910InstrPLA.json
diff --git
a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
index
22ea72f
..
862805a
100644
(file)
--- a/
plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
+++ b/
plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/am2910/Am2910InstrPLA.json
@@
-38,15
+38,6
@@
"logicWidth": 1,
"usage": "OUTPUT"
},
"logicWidth": 1,
"usage": "OUTPUT"
},
- {
- "location": {
- "x": 60.0,
- "y": 5.0
- },
- "name": "RLD",
- "logicWidth": 1,
- "usage": "OUTPUT"
- },
{
"location": {
"x": 60.0,
{
"location": {
"x": 60.0,
@@
-119,6
+110,15
@@
"logicWidth": 1,
"usage": "OUTPUT"
},
"logicWidth": 1,
"usage": "OUTPUT"
},
+ {
+ "location": {
+ "x": 60.0,
+ "y": 5.0
+ },
+ "name": "_RLD",
+ "logicWidth": 1,
+ "usage": "OUTPUT"
+ },
{
"location": {
"x": 45.0,
{
"location": {
"x": 45.0,
@@
-762,6
+762,15
@@
},
"params": 1
},
},
"params": 1
},
+ {
+ "id": "NandGate",
+ "name": "NandGate#70",
+ "pos": {
+ "x": 390.0,
+ "y": 40.0
+ },
+ "params": 1
+ },
{
"id": "Splitter",
"name": "Splitter#0",
{
"id": "Splitter",
"name": "Splitter#0",
@@
-1706,15
+1715,15
@@
"name": "and#9",
"pos": {
"x": 355.0,
"name": "and#9",
"pos": {
"x": 355.0,
- "y": 4
5
.0
+ "y": 4
0
.0
}
},
{
"id": "and",
"name": "and#10",
"pos": {
}
},
{
"id": "and",
"name": "and#10",
"pos": {
- "x": 3
90
.0,
- "y": 4
5
.0
+ "x": 3
85
.0,
+ "y": 4
30
.0
}
},
{
}
},
{
@@
-1772,14
+1781,6
@@
"x": 415.0,
"y": 345.0
}
"x": 415.0,
"y": 345.0
}
- },
- {
- "id": "and",
- "name": "and#18",
- "pos": {
- "x": 385.0,
- "y": 430.0
- }
}
],
"wires": [
}
],
"wires": [
@@
-2724,12
+2725,12
@@
},
{
"pin1": {
},
{
"pin1": {
- "compName": "
and#1
0",
+ "compName": "
NandGate#7
0",
"pinName": "Y"
},
"pin2": {
"compName": "_submodelinterface",
"pinName": "Y"
},
"pin2": {
"compName": "_submodelinterface",
- "pinName": "RLD"
+ "pinName": "
_
RLD"
},
"name": "unnamedWire#64",
"path": []
},
"name": "unnamedWire#64",
"path": []
@@
-2752,7
+2753,7
@@
"pinName": "Y"
},
"pin2": {
"pinName": "Y"
},
"pin2": {
- "compName": "
and#1
0",
+ "compName": "
NandGate#7
0",
"pinName": "A"
},
"name": "unnamedWire#66",
"pinName": "A"
},
"name": "unnamedWire#66",
@@
-3263,7
+3264,7
@@
},
{
"x": 350.0,
},
{
"x": 350.0,
- "y":
50
.0
+ "y":
45
.0
}
]
},
}
]
},
@@
-4200,7
+4201,7
@@
},
{
"pin1": {
},
{
"pin1": {
- "compName": "
and#1
0",
+ "compName": "
NandGate#7
0",
"pinName": "B"
},
"pin2": {
"pinName": "B"
},
"pin2": {
@@
-4211,7
+4212,7
@@
"path": [
{
"x": 385.0,
"path": [
{
"x": 385.0,
- "y":
60
.0
+ "y":
55
.0
},
{
"x": 385.0,
},
{
"x": 385.0,
@@
-5307,7
+5308,7
@@
"pinName": ""
},
"pin2": {
"pinName": ""
},
"pin2": {
- "compName": "and#1
8
",
+ "compName": "and#1
0
",
"pinName": "A"
},
"name": "unnamedWire#227",
"pinName": "A"
},
"name": "unnamedWire#227",
@@
-5319,7
+5320,7
@@
"pinName": ""
},
"pin2": {
"pinName": ""
},
"pin2": {
- "compName": "and#1
8
",
+ "compName": "and#1
0
",
"pinName": "B"
},
"name": "unnamedWire#228",
"pinName": "B"
},
"name": "unnamedWire#228",
@@
-5327,7
+5328,7
@@
},
{
"pin1": {
},
{
"pin1": {
- "compName": "and#1
8
",
+ "compName": "and#1
0
",
"pinName": "Y"
},
"pin2": {
"pinName": "Y"
},
"pin2": {
@@
-5654,7
+5655,7
@@
"path": [
{
"x": 350.0,
"path": [
{
"x": 350.0,
- "y":
60
.0
+ "y":
55
.0
}
]
},
}
]
},