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Implemented the STKI0 output of the Am2910InstrPLA in gates; w/o layout
[Mograsim.git]
/
plugins
/
net.mograsim.logic.model.am2900
/
components
/
net
/
mograsim
/
logic
/
model
/
am2900
/
components
/
mux1.json
diff --git
a/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/mux1.json
b/plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/mux1.json
index
3997209
..
241afab
100644
(file)
--- a/
plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/mux1.json
+++ b/
plugins/net.mograsim.logic.model.am2900/components/net/mograsim/logic/model/am2900/components/mux1.json
@@
-122,17
+122,6
@@
"name": "unnamedWire#1",
"path": []
},
"name": "unnamedWire#1",
"path": []
},
- {
- "pin1": {
- "compName": "NandGate#3",
- "pinName": "Y"
- },
- "pin2": {
- "compName": "_submodelinterface",
- "pinName": "Y"
- },
- "name": "unnamedWire#10"
- },
{
"pin1": {
"compName": "WireCrossPoint#0",
{
"pin1": {
"compName": "WireCrossPoint#0",
@@
-230,6
+219,17
@@
"pinName": "B"
},
"name": "unnamedWire#9"
"pinName": "B"
},
"name": "unnamedWire#9"
+ },
+ {
+ "pin1": {
+ "compName": "NandGate#3",
+ "pinName": "Y"
+ },
+ "pin2": {
+ "compName": "_submodelinterface",
+ "pinName": "Y"
+ },
+ "name": "unnamedWire#10"
}
],
"version": "0.1.1"
}
],
"version": "0.1.1"