Completion of ReadEnd and ReadWriteEnd addition

[Mograsim.git] / era.mi / src / era / mi / logic / components / BasicComponent.java

diff --git a/era.mi/src/era/mi/logic/components/BasicComponent.java b/era.mi/src/era/mi/logic/components/BasicComponent.java
index 7cebc60..f89a72c 100644 (file)
--- a/era.mi/src/era/mi/logic/components/BasicComponent.java
+++ b/era.mi/src/era/mi/logic/components/BasicComponent.java
@@ -1,8 +1,8 @@
 package era.mi.logic.components;
 
-import era.mi.logic.Bit;
 import era.mi.logic.Simulation;
-import era.mi.logic.wires.Wire;
+import era.mi.logic.types.BitVector;
+import era.mi.logic.wires.Wire.ReadEnd;
 import era.mi.logic.wires.WireObserver;
 
 /**
@@ -26,7 +26,7 @@ public abstract class BasicComponent implements WireObserver, Component
        }
 
        @Override
-       public void update(Wire initiator, Bit[] oldValues)
+       public void update(ReadEnd initiator, BitVector oldValues)
        {
                Simulation.TIMELINE.addEvent(e -> compute(), processTime);
        }