package era.mi.logic.components.gates;\r
\r
+import era.mi.logic.timeline.Timeline;\r
import era.mi.logic.types.BitVector.BitVectorMutator;\r
import era.mi.logic.wires.Wire.ReadEnd;\r
import era.mi.logic.wires.Wire.ReadWriteEnd;\r
\r
public class AndGate extends MultiInputGate\r
{\r
- public AndGate(int processTime, ReadWriteEnd out, ReadEnd... in)\r
+ public AndGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)\r
{\r
- super(processTime, BitVectorMutator::and, out, in);\r
+ super(timeline, processTime, BitVectorMutator::and, out, in);\r
}\r
}\r