WireEnd functionality split into ReadEnd and ReadWriteEnd

[Mograsim.git] / era.mi / src / era / mi / logic / components / gates / AndGate.java

diff --git a/era.mi/src/era/mi/logic/components/gates/AndGate.java b/era.mi/src/era/mi/logic/components/gates/AndGate.java
index 5da680e..e045982 100644 (file)
--- a/era.mi/src/era/mi/logic/components/gates/AndGate.java
+++ b/era.mi/src/era/mi/logic/components/gates/AndGate.java
@@ -1,11 +1,12 @@
 package era.mi.logic.components.gates;
 
 import era.mi.logic.types.BitVector.BitVectorMutator;
-import era.mi.logic.wires.Wire.WireEnd;
+import era.mi.logic.wires.Wire.ReadEnd;
+import era.mi.logic.wires.Wire.ReadWriteEnd;
 
 public class AndGate extends MultiInputGate
 {
-       public AndGate(int processTime, WireEnd out, WireEnd... in)
+       public AndGate(int processTime, ReadWriteEnd out, ReadEnd... in)
        {
                super(processTime, BitVectorMutator::and, out, in);
        }