package era.mi.logic.components.gates;\r
\r
+import era.mi.logic.timeline.Timeline;\r
import era.mi.logic.types.BitVector.BitVectorMutator;\r
-import era.mi.logic.wires.Wire.WireEnd;\r
+import era.mi.logic.wires.Wire.ReadEnd;\r
+import era.mi.logic.wires.Wire.ReadWriteEnd;\r
\r
/**\r
* Outputs 1 when the number of 1 inputs is odd.\r
*/\r
public class XorGate extends MultiInputGate\r
{\r
- public XorGate(int processTime, WireEnd out, WireEnd... in)\r
+ public XorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)\r
{\r
- super(processTime, BitVectorMutator::xor, out, in);\r
+ super(timeline, processTime, BitVectorMutator::xor, out, in);\r
}\r
\r
}\r