Suppressed warnings where the thing warned about is intentional

[Mograsim.git] / era.mi / src / era / mi / logic / components / gates / XorGate.java

diff --git a/era.mi/src/era/mi/logic/components/gates/XorGate.java b/era.mi/src/era/mi/logic/components/gates/XorGate.java
index c20af6f..2067a86 100644 (file)
--- a/era.mi/src/era/mi/logic/components/gates/XorGate.java
+++ b/era.mi/src/era/mi/logic/components/gates/XorGate.java
@@ -1,17 +1,20 @@
-package era.mi.logic.components.gates;
-
-import era.mi.logic.Util;
-import era.mi.logic.wires.WireArray;
-
-/**
- * Outputs 1 when the number of 1 inputs is odd.
- * @author Fabian Stemmler
- */
-public class XorGate extends MultiInputGate
-{      
-       public XorGate(int processTime, WireArray out, WireArray... in)
-       {
-               super(processTime, Util::xor, out, in);
-       }
-
-}
+package era.mi.logic.components.gates;\r
+\r
+import era.mi.logic.timeline.Timeline;\r
+import era.mi.logic.types.BitVector.BitVectorMutator;\r
+import era.mi.logic.wires.Wire.ReadEnd;\r
+import era.mi.logic.wires.Wire.ReadWriteEnd;\r
+\r
+/**\r
+ * Outputs 1 when the number of 1 inputs is odd.\r
+ * \r
+ * @author Fabian Stemmler\r
+ */\r
+public class XorGate extends MultiInputGate\r
+{\r
+       public XorGate(Timeline timeline, int processTime, ReadWriteEnd out, ReadEnd... in)\r
+       {\r
+               super(timeline, processTime, BitVectorMutator::xor, out, in);\r
+       }\r
+\r
+}\r