WireEnd functionality split into ReadEnd and ReadWriteEnd

[Mograsim.git] / era.mi / src / era / mi / logic / components / gates / XorGate.java

diff --git a/era.mi/src/era/mi/logic/components/gates/XorGate.java b/era.mi/src/era/mi/logic/components/gates/XorGate.java
index 73a2556..7c8d740 100644 (file)
--- a/era.mi/src/era/mi/logic/components/gates/XorGate.java
+++ b/era.mi/src/era/mi/logic/components/gates/XorGate.java
@@ -1,7 +1,8 @@
 package era.mi.logic.components.gates;
 
 import era.mi.logic.types.BitVector.BitVectorMutator;
-import era.mi.logic.wires.Wire.WireEnd;
+import era.mi.logic.wires.Wire.ReadEnd;
+import era.mi.logic.wires.Wire.ReadWriteEnd;
 
 /**
  * Outputs 1 when the number of 1 inputs is odd.
@@ -10,7 +11,7 @@ import era.mi.logic.wires.Wire.WireEnd;
  */
 public class XorGate extends MultiInputGate
 {
-       public XorGate(int processTime, WireEnd out, WireEnd... in)
+       public XorGate(int processTime, ReadWriteEnd out, ReadEnd... in)
        {
                super(processTime, BitVectorMutator::xor, out, in);
        }