import static org.junit.jupiter.api.Assertions.assertArrayEquals;
import static org.junit.jupiter.api.Assertions.assertEquals;
-import static org.junit.jupiter.api.Assertions.assertTrue;
import static org.junit.jupiter.api.Assertions.fail;
-import java.util.Arrays;
import java.util.function.LongConsumer;
import org.junit.jupiter.api.Test;
-import era.mi.logic.Bit;
import era.mi.logic.Simulation;
import era.mi.logic.components.Connector;
import era.mi.logic.components.Demux;
import era.mi.logic.components.gates.NotGate;
import era.mi.logic.components.gates.OrGate;
import era.mi.logic.components.gates.XorGate;
+import era.mi.logic.types.Bit;
+import era.mi.logic.types.BitVector;
import era.mi.logic.wires.Wire;
-import era.mi.logic.wires.Wire.WireEnd;
+import era.mi.logic.wires.Wire.ReadEnd;
+import era.mi.logic.wires.Wire.ReadWriteEnd;
-@SuppressWarnings("unused")
class ComponentTest
{
Simulation.TIMELINE.reset();
Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1),
g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1);
- new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd());
- new NotGate(1, f.createEnd(), g.createEnd());
- new Merger(h.createEnd(), c.createEnd(), g.createEnd());
- new Mux(1, i.createEnd(), e.createEnd(), h.createEnd(), d.createEnd());
- new Splitter(i.createEnd(), k.createEnd(), j.createEnd());
+ new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());
+ new NotGate(1, f.createReadOnlyEnd(), g.createEnd());
+ new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());
+ new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());
+ new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd());
a.createEnd().feedSignals(Bit.ZERO);
b.createEnd().feedSignals(Bit.ONE);
Simulation.TIMELINE.reset();
Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1);
in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
- new Splitter(in.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());
+ new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());
Simulation.TIMELINE.executeAll();
b.createEnd().feedSignals(Bit.ONE, Bit.ZERO);
c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);
- new Merger(out.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());
+ new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());
Simulation.TIMELINE.executeAll();
- assertTrue(
- Arrays.equals(out.getValues(), new Bit[] { Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE }));
+ assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
}
@Test
void triStateBufferTest()
{
Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1);
- new NotGate(1, en.createEnd(), notEn.createEnd());
- new TriStateBuffer(1, a.createEnd(), b.createEnd(), en.createEnd());
- new TriStateBuffer(1, b.createEnd(), a.createEnd(), notEn.createEnd());
+ new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd());
+ new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd());
+ new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd());
- WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();
+ ReadWriteEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();
enI.feedSignals(Bit.ONE);
aI.feedSignals(Bit.ONE);
bI.feedSignals(Bit.Z);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), out = new Wire(4, 1);
- WireEnd selectIn = select.createEnd();
+ ReadWriteEnd selectIn = select.createEnd();
selectIn.feedSignals(Bit.ZERO, Bit.ZERO);
a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);
c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
- new Mux(1, out.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());
+ new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());
Simulation.TIMELINE.executeAll();
assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), in = new Wire(4, 1);
- WireEnd selectIn = select.createEnd();
+ ReadWriteEnd selectIn = select.createEnd();
selectIn.feedSignals(Bit.ZERO, Bit.ZERO);
in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);
- new Demux(1, in.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());
+ new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());
Simulation.TIMELINE.executeAll();
assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);
- new AndGate(1, c.createEnd(), a.createEnd(), b.createEnd());
+ new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());
a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);
- new OrGate(1, c.createEnd(), a.createEnd(), b.createEnd());
+ new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());
a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);
b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1);
- new XorGate(1, d.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());
+ new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());
a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);
b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);
c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);
{
Simulation.TIMELINE.reset();
Wire a = new Wire(3, 1), b = new Wire(3, 2);
- new NotGate(1, a.createEnd(), b.createEnd());
+ new NotGate(1, a.createReadOnlyEnd(), b.createEnd());
a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);
Simulation.TIMELINE.executeAll();
Simulation.TIMELINE.reset();
Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1);
- new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd());
- new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd());
- new NotGate(1, t2.createEnd(), q.createEnd());
- new NotGate(1, t1.createEnd(), nq.createEnd());
+ new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());
+ new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());
+ new NotGate(1, t2.createReadOnlyEnd(), q.createEnd());
+ new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd());
- WireEnd sIn = s.createEnd(), rIn = r.createEnd();
+ ReadWriteEnd sIn = s.createEnd(), rIn = r.createEnd();
sIn.feedSignals(Bit.ONE);
rIn.feedSignals(Bit.ZERO);
{
Simulation.TIMELINE.reset();
Wire w = new Wire(2, 1);
- WireEnd wI1 = w.createEnd(), wI2 = w.createEnd();
+ ReadWriteEnd wI1 = w.createEnd(), wI2 = w.createEnd();
wI1.feedSignals(Bit.ONE, Bit.Z);
wI2.feedSignals(Bit.Z, Bit.X);
Simulation.TIMELINE.executeAll();
assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);
wI2.feedSignals(Bit.ONE, Bit.Z);
- w.addObserver((i, oldValues) -> fail("WireArray notified observer, although value did not change."));
+ ReadEnd rE = w.createReadOnlyEnd();
+ rE.addObserver((i, oldValues) -> fail("WireEnd notified observer, although value did not change."));
Simulation.TIMELINE.executeAll();
+ rE.close();
+ wI1.feedSignals(Bit.X, Bit.X);
+ Simulation.TIMELINE.executeAll();
+ wI1.addObserver((i, oldValues) -> fail("WireEnd notified observer, although it was closed."));
+ wI1.close();
assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);
}
Wire a = new Wire(1, 2);
Wire b = new Wire(1, 2);
Wire c = new Wire(1, 2);
- WireEnd aI = a.createEnd();
- WireEnd bI = b.createEnd();
- WireEnd cI = c.createEnd();
+ ReadWriteEnd aI = a.createEnd();
+ ReadWriteEnd bI = b.createEnd();
+ ReadWriteEnd cI = c.createEnd();
- TestBitDisplay test = new TestBitDisplay(c.createEnd());
- TestBitDisplay test2 = new TestBitDisplay(a.createEnd());
+ TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd());
+ TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd());
LongConsumer print = time -> System.out.format("Time %2d\n a: %s\n b: %s\n c: %s\n", time, a, b, c);
cI.feedSignals(Bit.ONE);
test2.assertAfterSimulationIs(Bit.ONE);
}
- private static void assertBitArrayEquals(Bit[] actual, Bit... expected)
+ private static void assertBitArrayEquals(BitVector actual, Bit... expected)
{
- assertArrayEquals(expected, actual);
+ assertArrayEquals(expected, actual.getBits());
}
}
projects / Mograsim.git / blobdiff