logic gates and, or and xor now take an arbitrary amount of inputs.

[Mograsim.git] / era.mi / src / era / mi / logic / tests / ComponentTest.java

diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java
index c233552..4f6826b 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/ComponentTest.java
+++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java
@@ -17,6 +17,7 @@ import era.mi.logic.components.TriStateBuffer;
 import era.mi.logic.components.gates.AndGate;\r
 import era.mi.logic.components.gates.NotGate;\r
 import era.mi.logic.components.gates.OrGate;\r
+import era.mi.logic.components.gates.XorGate;\r
 import era.mi.logic.wires.WireArray;\r
 import era.mi.logic.wires.WireArray.WireArrayInput;\r
 \r
@@ -29,7 +30,7 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                WireArray a = new WireArray(1, 1), b = new WireArray(1, 1), c = new WireArray(1, 10), d = new WireArray(2, 1), e = new WireArray(1, 1),\r
                                f = new WireArray(1, 1), g = new WireArray(1, 1), h = new WireArray(2, 1), i = new WireArray(2, 1), j = new WireArray(1, 1), k = new WireArray(1, 1);\r
-               new AndGate(1, a, b, f);\r
+               new AndGate(1, f, a, b);\r
                new NotGate(1, f, g);\r
                new Merger(h, c, g);\r
                new Mux(1, i, e, h, d);\r
@@ -177,25 +178,43 @@ class ComponentTest
     void andTest()\r
     {\r
        Simulation.TIMELINE.reset();\r
-       AndGate gate = new AndGate(1, new WireArray(4, 1), new WireArray(4, 1), new WireArray(4, 1));\r
-       gate.getA().createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
-       gate.getB().createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+       WireArray a = new WireArray(4, 1), b = new WireArray(4, 3), c = new WireArray(4, 1);\r
+       new AndGate(1, c, a, b);\r
+       a.createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+       b.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
        Simulation.TIMELINE.executeAll();\r
-       assertBitArrayEquals(gate.getOut().getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+       \r
+       assertBitArrayEquals(c.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
     }\r
 \r
     @Test\r
     void orTest()\r
     {\r
        Simulation.TIMELINE.reset();\r
-       OrGate gate = new OrGate(1, new WireArray(4, 1), new WireArray(4, 1), new WireArray(4, 1));\r
-       gate.getA().createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
-       gate.getB().createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+       WireArray a = new WireArray(4, 1), b = new WireArray(4, 3), c = new WireArray(4, 1);\r
+       new OrGate(1, c, a, b);\r
+       a.createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+       b.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
        Simulation.TIMELINE.executeAll();\r
 \r
-       assertBitArrayEquals(gate.getOut().getValues(), Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+       assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+    }\r
+    \r
+    @Test\r
+    void xorTest()\r
+    {\r
+       Simulation.TIMELINE.reset();\r
+       WireArray a = new WireArray(3, 1), b = new WireArray(3, 2), c = new WireArray(3, 1), d = new WireArray(3, 1);\r
+       new XorGate(1, d, a, b, c);\r
+       a.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
+       b.createInput().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+       c.createInput().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+\r
+       Simulation.TIMELINE.executeAll();\r
+\r
+       assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ONE, Bit.ONE);\r
     }\r
 \r
     @Test\r
@@ -205,8 +224,8 @@ class ComponentTest
        WireArray r = new WireArray(1, 1), s = new WireArray(1, 1), t1 = new WireArray(1, 15), t2 = new WireArray(1, 1),\r
                q = new WireArray(1, 1), nq = new WireArray(1, 1);\r
 \r
-       new OrGate(1, r, nq, t2);\r
-       new OrGate(1, s, q, t1);\r
+       new OrGate(1, t2, r, nq);\r
+       new OrGate(1, t1, s, q);\r
        new NotGate(1, t2, q);\r
        new NotGate(1, t1, nq);\r
 \r
@@ -301,7 +320,7 @@ class ComponentTest
                cI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               Connector c1 = new Connector(b, c);\r
+               new Connector(b, c);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
                System.err.println("ONE");\r
                bI.feedSignals(Bit.ONE);\r
@@ -313,7 +332,7 @@ class ComponentTest
                bI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
                \r
-               Connector c2 = new Connector(a, b);\r
+               new Connector(a, b);\r
                System.err.println("Z 2");\r
                aI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r