Exchanged all Bit[] by BitVector, tests work

[Mograsim.git] / era.mi / src / era / mi / logic / tests / ComponentTest.java

diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java
index d4ba21d..d25de9e 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/ComponentTest.java
+++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java
@@ -1,16 +1,11 @@
 package era.mi.logic.tests;\r
 \r
-import static org.junit.jupiter.api.Assertions.assertArrayEquals;\r
-import static org.junit.jupiter.api.Assertions.assertEquals;\r
-import static org.junit.jupiter.api.Assertions.assertTrue;\r
-import static org.junit.jupiter.api.Assertions.fail;\r
+import static org.junit.jupiter.api.Assertions.*;\r
 \r
-import java.util.Arrays;\r
 import java.util.function.LongConsumer;\r
 \r
 import org.junit.jupiter.api.Test;\r
 \r
-import era.mi.logic.Bit;\r
 import era.mi.logic.Simulation;\r
 import era.mi.logic.components.Connector;\r
 import era.mi.logic.components.Demux;\r
@@ -22,6 +17,8 @@ import era.mi.logic.components.gates.AndGate;
 import era.mi.logic.components.gates.NotGate;\r
 import era.mi.logic.components.gates.OrGate;\r
 import era.mi.logic.components.gates.XorGate;\r
+import era.mi.logic.types.Bit;\r
+import era.mi.logic.types.BitVector;\r
 import era.mi.logic.wires.Wire;\r
 import era.mi.logic.wires.Wire.WireEnd;\r
 \r
@@ -35,11 +32,11 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1),\r
                                g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1);\r
-               new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd());\r
-               new NotGate(1, f.createEnd(), g.createEnd());\r
-               new Merger(h.createEnd(), c.createEnd(), g.createEnd());\r
-               new Mux(1, i.createEnd(), e.createEnd(), h.createEnd(), d.createEnd());\r
-               new Splitter(i.createEnd(), k.createEnd(), j.createEnd());\r
+               new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+               new NotGate(1, f.createReadOnlyEnd(), g.createEnd());\r
+               new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());\r
+               new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());\r
+               new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd());\r
 \r
                a.createEnd().feedSignals(Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ONE);\r
@@ -59,7 +56,7 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1);\r
                in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
-               new Splitter(in.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -77,21 +74,20 @@ class ComponentTest
                b.createEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
                c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Merger(out.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
-               assertTrue(\r
-                               Arrays.equals(out.getValues(), new Bit[] { Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE }));\r
+               assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
        }\r
 \r
        @Test\r
        void triStateBufferTest()\r
        {\r
                Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1);\r
-               new NotGate(1, en.createEnd(), notEn.createEnd());\r
-               new TriStateBuffer(1, a.createEnd(), b.createEnd(), en.createEnd());\r
-               new TriStateBuffer(1, b.createEnd(), a.createEnd(), notEn.createEnd());\r
+               new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd());\r
+               new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd());\r
+               new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd());\r
 \r
                WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();\r
                enI.feedSignals(Bit.ONE);\r
@@ -129,7 +125,7 @@ class ComponentTest
                a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
                c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Mux(1, out.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -155,7 +151,7 @@ class ComponentTest
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
                in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
 \r
-               new Demux(1, in.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -182,7 +178,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new AndGate(1, c.createEnd(), a.createEnd(), b.createEnd());\r
+               new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
@@ -196,7 +192,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new OrGate(1, c.createEnd(), a.createEnd(), b.createEnd());\r
+               new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
@@ -210,7 +206,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1);\r
-               new XorGate(1, d.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
                b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
                c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
@@ -225,7 +221,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2);\r
-               new NotGate(1, a.createEnd(), b.createEnd());\r
+               new NotGate(1, a.createReadOnlyEnd(), b.createEnd());\r
                a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
@@ -239,10 +235,10 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1);\r
 \r
-               new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd());\r
-               new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd());\r
-               new NotGate(1, t2.createEnd(), q.createEnd());\r
-               new NotGate(1, t1.createEnd(), nq.createEnd());\r
+               new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
+               new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
+               new NotGate(1, t2.createReadOnlyEnd(), q.createEnd());\r
+               new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd());\r
 \r
                WireEnd sIn = s.createEnd(), rIn = r.createEnd();\r
 \r
@@ -321,8 +317,8 @@ class ComponentTest
                WireEnd bI = b.createEnd();\r
                WireEnd cI = c.createEnd();\r
 \r
-               TestBitDisplay test = new TestBitDisplay(c.createEnd());\r
-               TestBitDisplay test2 = new TestBitDisplay(a.createEnd());\r
+               TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd());\r
+               TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd());\r
                LongConsumer print = time -> System.out.format("Time %2d\n   a: %s\n   b: %s\n   c: %s\n", time, a, b, c);\r
 \r
                cI.feedSignals(Bit.ONE);\r
@@ -381,8 +377,8 @@ class ComponentTest
                test2.assertAfterSimulationIs(Bit.ONE);\r
        }\r
 \r
-       private static void assertBitArrayEquals(Bit[] actual, Bit... expected)\r
+       private static void assertBitArrayEquals(BitVector actual, Bit... expected)\r
        {\r
-               assertArrayEquals(expected, actual);\r
+               assertArrayEquals(expected, actual.getBits());\r
        }\r
 }\r