Integrated new types, tests still work, not used yet

[Mograsim.git] / era.mi / src / era / mi / logic / tests / ComponentTest.java

diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java
index 174deb4..d2be9b7 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/ComponentTest.java
+++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java
@@ -7,8 +7,8 @@ import java.util.function.LongConsumer;
 \r
 import org.junit.jupiter.api.Test;\r
 \r
-import era.mi.logic.Bit;\r
 import era.mi.logic.Simulation;\r
+import era.mi.logic.components.Connector;\r
 import era.mi.logic.components.Demux;\r
 import era.mi.logic.components.Merger;\r
 import era.mi.logic.components.Mux;\r
@@ -18,9 +18,11 @@ import era.mi.logic.components.gates.AndGate;
 import era.mi.logic.components.gates.NotGate;\r
 import era.mi.logic.components.gates.OrGate;\r
 import era.mi.logic.components.gates.XorGate;\r
+import era.mi.logic.types.Bit;\r
 import era.mi.logic.wires.Wire;\r
 import era.mi.logic.wires.Wire.WireEnd;\r
 \r
+@SuppressWarnings("unused")\r
 class ComponentTest\r
 {\r
 \r
@@ -28,14 +30,13 @@ class ComponentTest
        void circuitExampleTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1),\r
-                               e = new Wire(1, 1), f = new Wire(1, 1), g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1),\r
-                               j = new Wire(1, 1), k = new Wire(1, 1);\r
-               new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd());\r
-               new NotGate(1, f.createEnd(), g.createEnd());\r
-               new Merger(h.createEnd(), c.createEnd(), g.createEnd());\r
-               new Mux(1, i.createEnd(), e.createEnd(), h.createEnd(), d.createEnd());\r
-               new Splitter(i.createEnd(), k.createEnd(), j.createEnd());\r
+               Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1),\r
+                               g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1);\r
+               new AndGate(1, f.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+               new NotGate(1, f.createReadOnlyEnd(), g.createEnd());\r
+               new Merger(h.createEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());\r
+               new Mux(1, i.createEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());\r
+               new Splitter(i.createReadOnlyEnd(), k.createEnd(), j.createEnd());\r
 \r
                a.createEnd().feedSignals(Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ONE);\r
@@ -55,7 +56,7 @@ class ComponentTest
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(2, 1), c = new Wire(3, 1), in = new Wire(8, 1);\r
                in.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
-               new Splitter(in.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Splitter(in.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -73,7 +74,7 @@ class ComponentTest
                b.createEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
                c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Merger(out.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Merger(out.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -85,13 +86,14 @@ class ComponentTest
        void triStateBufferTest()\r
        {\r
                Wire a = new Wire(1, 1), b = new Wire(1, 1), en = new Wire(1, 1), notEn = new Wire(1, 1);\r
-               new NotGate(1, en.createEnd(), notEn.createEnd());\r
-               new TriStateBuffer(1, a.createEnd(), b.createEnd(), en.createEnd());\r
-               new TriStateBuffer(1, b.createEnd(), a.createEnd(), notEn.createEnd());\r
+               new NotGate(1, en.createReadOnlyEnd(), notEn.createEnd());\r
+               new TriStateBuffer(1, a.createReadOnlyEnd(), b.createEnd(), en.createReadOnlyEnd());\r
+               new TriStateBuffer(1, b.createReadOnlyEnd(), a.createEnd(), notEn.createReadOnlyEnd());\r
 \r
                WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();\r
                enI.feedSignals(Bit.ONE);\r
                aI.feedSignals(Bit.ONE);\r
+               bI.feedSignals(Bit.Z);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -117,15 +119,14 @@ class ComponentTest
        void muxTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5),\r
-                               out = new Wire(4, 1);\r
+               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), out = new Wire(4, 1);\r
                WireEnd selectIn = select.createEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
                a.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
                c.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
-               new Mux(1, out.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Mux(1, out.createEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -145,14 +146,13 @@ class ComponentTest
        void demuxTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5),\r
-                               in = new Wire(4, 1);\r
+               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), in = new Wire(4, 1);\r
                WireEnd selectIn = select.createEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
                in.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
 \r
-               new Demux(1, in.createEnd(), select.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new Demux(1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
                Simulation.TIMELINE.executeAll();\r
 \r
                assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
@@ -179,7 +179,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new AndGate(1, c.createEnd(), a.createEnd(), b.createEnd());\r
+               new AndGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
@@ -193,7 +193,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(4, 1), b = new Wire(4, 3), c = new Wire(4, 1);\r
-               new OrGate(1, c.createEnd(), a.createEnd(), b.createEnd());\r
+               new OrGate(1, c.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
                b.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
 \r
@@ -207,7 +207,7 @@ class ComponentTest
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2), c = new Wire(3, 1), d = new Wire(3, 1);\r
-               new XorGate(1, d.createEnd(), a.createEnd(), b.createEnd(), c.createEnd());\r
+               new XorGate(1, d.createEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
                a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
                b.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
                c.createEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
@@ -216,13 +216,13 @@ class ComponentTest
 \r
                assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ONE, Bit.ONE);\r
        }\r
-       \r
+\r
        @Test\r
        void notTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
                Wire a = new Wire(3, 1), b = new Wire(3, 2);\r
-               new NotGate(1, a.createEnd(), b.createEnd());\r
+               new NotGate(1, a.createReadOnlyEnd(), b.createEnd());\r
                a.createEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
 \r
                Simulation.TIMELINE.executeAll();\r
@@ -234,13 +234,12 @@ class ComponentTest
        void rsLatchCircuitTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1),\r
-                               q = new Wire(1, 1), nq = new Wire(1, 1);\r
+               Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1);\r
 \r
-               new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd());\r
-               new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd());\r
-               new NotGate(1, t2.createEnd(), q.createEnd());\r
-               new NotGate(1, t1.createEnd(), nq.createEnd());\r
+               new OrGate(1, t2.createEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
+               new OrGate(1, t1.createEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
+               new NotGate(1, t2.createReadOnlyEnd(), q.createEnd());\r
+               new NotGate(1, t1.createReadOnlyEnd(), nq.createEnd());\r
 \r
                WireEnd sIn = s.createEnd(), rIn = r.createEnd();\r
 \r
@@ -305,7 +304,7 @@ class ComponentTest
                assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
        }\r
 \r
-//     @Test\r
+       @Test\r
        void wireConnections()\r
        {\r
                // Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde\r
@@ -319,8 +318,8 @@ class ComponentTest
                WireEnd bI = b.createEnd();\r
                WireEnd cI = c.createEnd();\r
 \r
-               TestBitDisplay test = new TestBitDisplay(c.createEnd());\r
-               TestBitDisplay test2 = new TestBitDisplay(a.createEnd());\r
+               TestBitDisplay test = new TestBitDisplay(c.createReadOnlyEnd());\r
+               TestBitDisplay test2 = new TestBitDisplay(a.createReadOnlyEnd());\r
                LongConsumer print = time -> System.out.format("Time %2d\n   a: %s\n   b: %s\n   c: %s\n", time, a, b, c);\r
 \r
                cI.feedSignals(Bit.ONE);\r
@@ -333,7 +332,7 @@ class ComponentTest
                cI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(b, c);\r
+               new Connector(b.createEnd(), c.createEnd()).connect();\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
                System.err.println("ONE");\r
                bI.feedSignals(Bit.ONE);\r
@@ -345,7 +344,7 @@ class ComponentTest
                bI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(a, b);\r
+               new Connector(a.createEnd(), b.createEnd()).connect();\r
                System.err.println("Z 2");\r
                aI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r