Merge logic of origin into logic

[Mograsim.git] / era.mi / src / era / mi / logic / tests / ComponentTest.java

diff --git a/era.mi/src/era/mi/logic/tests/ComponentTest.java b/era.mi/src/era/mi/logic/tests/ComponentTest.java
index 174deb4..d4ba21d 100644 (file)
--- a/era.mi/src/era/mi/logic/tests/ComponentTest.java
+++ b/era.mi/src/era/mi/logic/tests/ComponentTest.java
@@ -1,6 +1,9 @@
 package era.mi.logic.tests;\r
 \r
-import static org.junit.jupiter.api.Assertions.*;\r
+import static org.junit.jupiter.api.Assertions.assertArrayEquals;\r
+import static org.junit.jupiter.api.Assertions.assertEquals;\r
+import static org.junit.jupiter.api.Assertions.assertTrue;\r
+import static org.junit.jupiter.api.Assertions.fail;\r
 \r
 import java.util.Arrays;\r
 import java.util.function.LongConsumer;\r
@@ -9,6 +12,7 @@ import org.junit.jupiter.api.Test;
 \r
 import era.mi.logic.Bit;\r
 import era.mi.logic.Simulation;\r
+import era.mi.logic.components.Connector;\r
 import era.mi.logic.components.Demux;\r
 import era.mi.logic.components.Merger;\r
 import era.mi.logic.components.Mux;\r
@@ -21,6 +25,7 @@ import era.mi.logic.components.gates.XorGate;
 import era.mi.logic.wires.Wire;\r
 import era.mi.logic.wires.Wire.WireEnd;\r
 \r
+@SuppressWarnings("unused")\r
 class ComponentTest\r
 {\r
 \r
@@ -28,9 +33,8 @@ class ComponentTest
        void circuitExampleTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1),\r
-                               e = new Wire(1, 1), f = new Wire(1, 1), g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1),\r
-                               j = new Wire(1, 1), k = new Wire(1, 1);\r
+               Wire a = new Wire(1, 1), b = new Wire(1, 1), c = new Wire(1, 10), d = new Wire(2, 1), e = new Wire(1, 1), f = new Wire(1, 1),\r
+                               g = new Wire(1, 1), h = new Wire(2, 1), i = new Wire(2, 1), j = new Wire(1, 1), k = new Wire(1, 1);\r
                new AndGate(1, f.createEnd(), a.createEnd(), b.createEnd());\r
                new NotGate(1, f.createEnd(), g.createEnd());\r
                new Merger(h.createEnd(), c.createEnd(), g.createEnd());\r
@@ -92,6 +96,7 @@ class ComponentTest
                WireEnd enI = en.createEnd(), aI = a.createEnd(), bI = b.createEnd();\r
                enI.feedSignals(Bit.ONE);\r
                aI.feedSignals(Bit.ONE);\r
+               bI.feedSignals(Bit.Z);\r
 \r
                Simulation.TIMELINE.executeAll();\r
 \r
@@ -117,8 +122,7 @@ class ComponentTest
        void muxTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5),\r
-                               out = new Wire(4, 1);\r
+               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), out = new Wire(4, 1);\r
                WireEnd selectIn = select.createEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
@@ -145,8 +149,7 @@ class ComponentTest
        void demuxTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5),\r
-                               in = new Wire(4, 1);\r
+               Wire a = new Wire(4, 3), b = new Wire(4, 6), c = new Wire(4, 4), select = new Wire(2, 5), in = new Wire(4, 1);\r
                WireEnd selectIn = select.createEnd();\r
 \r
                selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
@@ -216,7 +219,7 @@ class ComponentTest
 \r
                assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ONE, Bit.ONE);\r
        }\r
-       \r
+\r
        @Test\r
        void notTest()\r
        {\r
@@ -234,8 +237,7 @@ class ComponentTest
        void rsLatchCircuitTest()\r
        {\r
                Simulation.TIMELINE.reset();\r
-               Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1),\r
-                               q = new Wire(1, 1), nq = new Wire(1, 1);\r
+               Wire r = new Wire(1, 1), s = new Wire(1, 1), t1 = new Wire(1, 15), t2 = new Wire(1, 1), q = new Wire(1, 1), nq = new Wire(1, 1);\r
 \r
                new OrGate(1, t2.createEnd(), r.createEnd(), nq.createEnd());\r
                new OrGate(1, t1.createEnd(), s.createEnd(), q.createEnd());\r
@@ -305,7 +307,7 @@ class ComponentTest
                assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
        }\r
 \r
-//     @Test\r
+       @Test\r
        void wireConnections()\r
        {\r
                // Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde\r
@@ -333,7 +335,7 @@ class ComponentTest
                cI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(b, c);\r
+               new Connector(b.createEnd(), c.createEnd()).connect();\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
                System.err.println("ONE");\r
                bI.feedSignals(Bit.ONE);\r
@@ -345,7 +347,7 @@ class ComponentTest
                bI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r
 \r
-               new Connector(a, b);\r
+               new Connector(a.createEnd(), b.createEnd()).connect();\r
                System.err.println("Z 2");\r
                aI.feedSignals(Bit.Z);\r
                test.assertAfterSimulationIs(print, Bit.Z);\r