package era.mi.logic.tests;\r
\r
-import static org.junit.jupiter.api.Assertions.*;\r
+import static org.junit.Assert.assertTrue;\r
+import static org.junit.jupiter.api.Assertions.assertArrayEquals;\r
+import static org.junit.jupiter.api.Assertions.assertEquals;\r
+import static org.junit.jupiter.api.Assertions.fail;\r
\r
-import java.util.Arrays;\r
import java.util.function.LongConsumer;\r
\r
import org.junit.jupiter.api.Test;\r
\r
-import era.mi.logic.Bit;\r
-import era.mi.logic.Simulation;\r
+import era.mi.logic.components.Connector;\r
+import era.mi.logic.components.Demux;\r
import era.mi.logic.components.Merger;\r
import era.mi.logic.components.Mux;\r
import era.mi.logic.components.Splitter;\r
import era.mi.logic.components.gates.AndGate;\r
import era.mi.logic.components.gates.NotGate;\r
import era.mi.logic.components.gates.OrGate;\r
-import era.mi.logic.wires.WireArray;\r
-import era.mi.logic.wires.WireArray.WireArrayInput;\r
+import era.mi.logic.components.gates.XorGate;\r
+import era.mi.logic.timeline.Timeline;\r
+import era.mi.logic.types.Bit;\r
+import era.mi.logic.types.BitVector;\r
+import era.mi.logic.wires.Wire;\r
+import era.mi.logic.wires.Wire.ReadEnd;\r
+import era.mi.logic.wires.Wire.ReadWriteEnd;\r
\r
class ComponentTest\r
{\r
- \r
+ private Timeline t = new Timeline(11);\r
+\r
@Test\r
void circuitExampleTest()\r
{\r
- Simulation.TIMELINE.reset();\r
- WireArray a = new WireArray(1, 1), b = new WireArray(1, 1), c = new WireArray(1, 10), d = new WireArray(2, 1), e = new WireArray(1, 1),\r
- f = new WireArray(1, 1), g = new WireArray(1, 1), h = new WireArray(2, 1), i = new WireArray(2, 1), j = new WireArray(1, 1), k = new WireArray(1, 1);\r
- new AndGate(1, a, b, f);\r
- new NotGate(1, f, g);\r
- new Merger(h, c, g);\r
- new Mux(1, i, e, h, d);\r
- new Splitter(i, k, j);\r
- \r
- a.createInput().feedSignals(Bit.ZERO);\r
- b.createInput().feedSignals(Bit.ONE);\r
- c.createInput().feedSignals(Bit.ZERO);\r
- d.createInput().feedSignals(Bit.ONE, Bit.ONE);\r
- e.createInput().feedSignals(Bit.ZERO);\r
- \r
- Simulation.TIMELINE.executeAll();\r
- \r
+ Wire a = new Wire(t, 1, 1), b = new Wire(t, 1, 1), c = new Wire(t, 1, 10), d = new Wire(t, 2, 1), e = new Wire(t, 1, 1),\r
+ f = new Wire(t, 1, 1), g = new Wire(t, 1, 1), h = new Wire(t, 2, 1), i = new Wire(t, 2, 1), j = new Wire(t, 1, 1),\r
+ k = new Wire(t, 1, 1);\r
+ new AndGate(t, 1, f.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+ new NotGate(t, 1, f.createReadOnlyEnd(), g.createReadWriteEnd());\r
+ new Merger(t, h.createReadWriteEnd(), c.createReadOnlyEnd(), g.createReadOnlyEnd());\r
+ new Mux(t, 1, i.createReadWriteEnd(), e.createReadOnlyEnd(), h.createReadOnlyEnd(), d.createReadOnlyEnd());\r
+ new Splitter(t, i.createReadOnlyEnd(), k.createReadWriteEnd(), j.createReadWriteEnd());\r
+\r
+ a.createReadWriteEnd().feedSignals(Bit.ZERO);\r
+ b.createReadWriteEnd().feedSignals(Bit.ONE);\r
+ c.createReadWriteEnd().feedSignals(Bit.ZERO);\r
+ d.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE);\r
+ e.createReadWriteEnd().feedSignals(Bit.ZERO);\r
+\r
+ t.executeAll();\r
+\r
assertEquals(Bit.ONE, j.getValue());\r
assertEquals(Bit.ZERO, k.getValue());\r
}\r
\r
- @Test\r
- void splitterTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- WireArray a = new WireArray(3, 1), b = new WireArray(2, 1), c = new WireArray(3, 1), in = new WireArray(8, 1);\r
- in.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
- new Splitter(in, a, b, c);\r
+ @Test\r
+ void splitterTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), in = new Wire(t, 8, 1);\r
+ in.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ new Splitter(t, in.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(), c.createReadWriteEnd());\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertBitArrayEquals(a.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO);\r
- assertBitArrayEquals(b.getValues(), Bit.ONE, Bit.ZERO);\r
- assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE);\r
- }\r
+ assertBitArrayEquals(a.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+ assertBitArrayEquals(b.getValues(), Bit.ONE, Bit.ZERO);\r
+ assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ }\r
\r
- @Test\r
- void mergerTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- WireArray a = new WireArray(3, 1), b = new WireArray(2, 1), c = new WireArray(3, 1), out = new WireArray(8, 1);\r
- a.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);\r
- b.createInput().feedSignals(Bit.ONE, Bit.ZERO);\r
- c.createInput().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ @Test\r
+ void mergerTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 3, 1), b = new Wire(t, 2, 1), c = new Wire(t, 3, 1), out = new Wire(t, 8, 1);\r
+ a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+ b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO);\r
+ c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- new Merger(out, a, b, c);\r
+ new Merger(t, out.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertTrue(Arrays.equals(out.getValues(),\r
- new Bit[] { Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE }));\r
- }\r
+ assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ }\r
\r
- @Test\r
- void triStateBufferTest()\r
- {\r
- WireArray a = new WireArray(1, 1), b = new WireArray(1, 1), en = new WireArray(1, 1),\r
- notEn = new WireArray(1, 1);\r
- new NotGate(1, en, notEn);\r
- new TriStateBuffer(1, a, b, en);\r
- new TriStateBuffer(1, b, a, notEn);\r
+ @Test\r
+ void triStateBufferTest()\r
+ {\r
+ Wire a = new Wire(t, 1, 1), b = new Wire(t, 1, 1), en = new Wire(t, 1, 1), notEn = new Wire(t, 1, 1);\r
+ new NotGate(t, 1, en.createReadOnlyEnd(), notEn.createReadWriteEnd());\r
+ new TriStateBuffer(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd(), en.createReadOnlyEnd());\r
+ new TriStateBuffer(t, 1, b.createReadOnlyEnd(), a.createReadWriteEnd(), notEn.createReadOnlyEnd());\r
\r
- WireArrayInput enI = en.createInput(), aI = a.createInput(), bI = b.createInput();\r
- enI.feedSignals(Bit.ONE);\r
- aI.feedSignals(Bit.ONE);\r
+ ReadWriteEnd enI = en.createReadWriteEnd(), aI = a.createReadWriteEnd(), bI = b.createReadWriteEnd();\r
+ enI.feedSignals(Bit.ONE);\r
+ aI.feedSignals(Bit.ONE);\r
+ bI.feedSignals(Bit.Z);\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertEquals(Bit.ONE, b.getValue());\r
+ assertEquals(Bit.ONE, b.getValue());\r
\r
- bI.feedSignals(Bit.ZERO);\r
+ bI.feedSignals(Bit.ZERO);\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertEquals(Bit.X, b.getValue());\r
- assertEquals(Bit.ONE, a.getValue());\r
+ assertEquals(Bit.X, b.getValue());\r
+ assertEquals(Bit.ONE, a.getValue());\r
\r
- aI.clearSignals();\r
- enI.feedSignals(Bit.ZERO);\r
+ aI.clearSignals();\r
+ enI.feedSignals(Bit.ZERO);\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertEquals(Bit.ZERO, a.getValue());\r
+ assertEquals(Bit.ZERO, a.getValue());\r
\r
- }\r
+ }\r
\r
- @Test\r
- void muxTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- WireArray a = new WireArray(4, 3), b = new WireArray(4, 6), c = new WireArray(4, 4),\r
- select = new WireArray(2, 5), out = new WireArray(4, 1);\r
- WireArrayInput selectIn = select.createInput();\r
+ @Test\r
+ void muxTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), out = new Wire(t, 4, 1);\r
+ ReadWriteEnd selectIn = select.createReadWriteEnd();\r
\r
- selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
- a.createInput().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
- c.createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
+ a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+ c.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- new Mux(1, out, select, a, b, c);\r
- Simulation.TIMELINE.executeAll();\r
+ new Mux(t, 1, out.createReadWriteEnd(), select.createReadOnlyEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(),\r
+ c.createReadOnlyEnd());\r
+ t.executeAll();\r
\r
- assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
- selectIn.feedSignals(Bit.ZERO, Bit.ONE);\r
- Simulation.TIMELINE.executeAll();\r
+ assertBitArrayEquals(out.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+ selectIn.feedSignals(Bit.ZERO, Bit.ONE);\r
+ t.executeAll();\r
\r
- assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ assertBitArrayEquals(out.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- selectIn.feedSignals(Bit.ONE, Bit.ONE);\r
- Simulation.TIMELINE.executeAll();\r
+ selectIn.feedSignals(Bit.ONE, Bit.ONE);\r
+ t.executeAll();\r
\r
- assertBitArrayEquals(out.getValues(), Bit.Z, Bit.Z, Bit.Z, Bit.Z);\r
+ assertBitArrayEquals(out.getValues(), Bit.Z, Bit.Z, Bit.Z, Bit.Z);\r
\r
- }\r
+ }\r
\r
- @Test\r
- void andTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- AndGate gate = new AndGate(1, new WireArray(4, 1), new WireArray(4, 1), new WireArray(4, 1));\r
- gate.getA().createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
- gate.getB().createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ @Test\r
+ void demuxTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 4, 3), b = new Wire(t, 4, 6), c = new Wire(t, 4, 4), select = new Wire(t, 2, 5), in = new Wire(t, 4, 1);\r
+ ReadWriteEnd selectIn = select.createReadWriteEnd();\r
\r
- Simulation.TIMELINE.executeAll();\r
- assertBitArrayEquals(gate.getOut().getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
- }\r
+ selectIn.feedSignals(Bit.ZERO, Bit.ZERO);\r
+ in.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
\r
- @Test\r
- void orTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- OrGate gate = new OrGate(1, new WireArray(4, 1), new WireArray(4, 1), new WireArray(4, 1));\r
- gate.getA().createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
- gate.getB().createInput().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ new Demux(t, 1, in.createReadOnlyEnd(), select.createReadOnlyEnd(), a.createReadWriteEnd(), b.createReadWriteEnd(),\r
+ c.createReadWriteEnd());\r
+ t.executeAll();\r
\r
- Simulation.TIMELINE.executeAll();\r
+ assertBitArrayEquals(a.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
+ assertBitArrayEquals(b.getValues(), Bit.U, Bit.U, Bit.U, Bit.U);\r
+ assertBitArrayEquals(c.getValues(), Bit.U, Bit.U, Bit.U, Bit.U);\r
+ selectIn.feedSignals(Bit.ZERO, Bit.ONE);\r
+ t.executeAll();\r
\r
- assertBitArrayEquals(gate.getOut().getValues(), Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ONE);\r
- }\r
+ assertBitArrayEquals(a.getValues(), Bit.Z, Bit.Z, Bit.Z, Bit.Z);\r
+ assertBitArrayEquals(b.getValues(), Bit.U, Bit.U, Bit.U, Bit.U);\r
+ assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ZERO, Bit.ONE, Bit.ZERO);\r
\r
- @Test\r
- void rsLatchCircuitTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
- WireArray r = new WireArray(1, 1), s = new WireArray(1, 1), t1 = new WireArray(1, 15), t2 = new WireArray(1, 1),\r
- q = new WireArray(1, 1), nq = new WireArray(1, 1);\r
+ selectIn.feedSignals(Bit.ONE, Bit.ONE);\r
+ t.executeAll();\r
\r
- new OrGate(1, r, nq, t2);\r
- new OrGate(1, s, q, t1);\r
- new NotGate(1, t2, q);\r
- new NotGate(1, t1, nq);\r
+ assertBitArrayEquals(a.getValues(), Bit.Z, Bit.Z, Bit.Z, Bit.Z);\r
+ assertBitArrayEquals(b.getValues(), Bit.U, Bit.U, Bit.U, Bit.U);\r
+ assertBitArrayEquals(c.getValues(), Bit.Z, Bit.Z, Bit.Z, Bit.Z);\r
\r
- WireArrayInput sIn = s.createInput(), rIn = r.createInput();\r
+ }\r
\r
- sIn.feedSignals(Bit.ONE);\r
- rIn.feedSignals(Bit.ZERO);\r
+ @Test\r
+ void andTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1);\r
+ new AndGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+ a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+ b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertEquals(Bit.ONE, q.getValue());\r
- assertEquals(Bit.ZERO, nq.getValue());\r
+ assertBitArrayEquals(c.getValues(), Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+ }\r
\r
- sIn.feedSignals(Bit.ZERO);\r
+ @Test\r
+ void orTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 4, 1), b = new Wire(t, 4, 3), c = new Wire(t, 4, 1);\r
+ new OrGate(t, 1, c.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd());\r
+ a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+ b.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- Simulation.TIMELINE.executeAll();\r
- assertEquals(Bit.ONE, q.getValue());\r
- assertEquals(Bit.ZERO, nq.getValue());\r
+ t.executeAll();\r
\r
- rIn.feedSignals(Bit.ONE);\r
+ assertBitArrayEquals(c.getValues(), Bit.ONE, Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ }\r
\r
- Simulation.TIMELINE.executeAll();\r
+ @Test\r
+ void xorTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2), c = new Wire(t, 3, 1), d = new Wire(t, 3, 1);\r
+ new XorGate(t, 1, d.createReadWriteEnd(), a.createReadOnlyEnd(), b.createReadOnlyEnd(), c.createReadOnlyEnd());\r
+ a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
+ b.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
+ c.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ZERO, Bit.ONE);\r
\r
- assertEquals(Bit.ZERO, q.getValue());\r
- assertEquals(Bit.ONE, nq.getValue());\r
- }\r
+ t.executeAll();\r
\r
- @Test\r
- void numericValueTest()\r
- {\r
- Simulation.TIMELINE.reset();\r
+ assertBitArrayEquals(d.getValues(), Bit.ZERO, Bit.ONE, Bit.ONE);\r
+ }\r
\r
- WireArray a = new WireArray(4, 1);\r
- a.createInput().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE);\r
+ @Test\r
+ void notTest()\r
+ {\r
+ t.reset();\r
+ Wire a = new Wire(t, 3, 1), b = new Wire(t, 3, 2);\r
+ new NotGate(t, 1, a.createReadOnlyEnd(), b.createReadWriteEnd());\r
+ a.createReadWriteEnd().feedSignals(Bit.ZERO, Bit.ONE, Bit.ONE);\r
\r
- Simulation.TIMELINE.executeAll();\r
+ t.executeAll();\r
\r
- assertEquals(15, a.getUnsignedValue());\r
- assertEquals(-1, a.getSignedValue());\r
- }\r
+ assertBitArrayEquals(b.getValues(), Bit.ONE, Bit.ZERO, Bit.ZERO);\r
+ }\r
\r
- @Test\r
- void multipleInputs()\r
- {\r
- Simulation.TIMELINE.reset();\r
- WireArray w = new WireArray(2, 1);\r
- WireArrayInput wI1 = w.createInput(), wI2 = w.createInput();\r
- wI1.feedSignals(Bit.ONE, Bit.Z);\r
- wI2.feedSignals(Bit.Z, Bit.X);\r
- Simulation.TIMELINE.executeAll();\r
- assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.X);\r
+ @Test\r
+ void rsLatchCircuitTest()\r
+ {\r
+ t.reset();\r
+ Wire r = new Wire(t, 1, 1), s = new Wire(t, 1, 1), t1 = new Wire(t, 1, 15), t2 = new Wire(t, 1, 1), q = new Wire(t, 1, 1),\r
+ nq = new Wire(t, 1, 1);\r
+\r
+ new OrGate(t, 1, t2.createReadWriteEnd(), r.createReadOnlyEnd(), nq.createReadOnlyEnd());\r
+ new OrGate(t, 1, t1.createReadWriteEnd(), s.createReadOnlyEnd(), q.createReadOnlyEnd());\r
+ new NotGate(t, 1, t2.createReadOnlyEnd(), q.createReadWriteEnd());\r
+ new NotGate(t, 1, t1.createReadOnlyEnd(), nq.createReadWriteEnd());\r
+\r
+ ReadWriteEnd sIn = s.createReadWriteEnd(), rIn = r.createReadWriteEnd();\r
+\r
+ sIn.feedSignals(Bit.ONE);\r
+ rIn.feedSignals(Bit.ZERO);\r
+\r
+ t.executeAll();\r
+\r
+ assertEquals(Bit.ONE, q.getValue());\r
+ assertEquals(Bit.ZERO, nq.getValue());\r
+\r
+ sIn.feedSignals(Bit.ZERO);\r
+\r
+ t.executeAll();\r
+ assertEquals(Bit.ONE, q.getValue());\r
+ assertEquals(Bit.ZERO, nq.getValue());\r
+\r
+ rIn.feedSignals(Bit.ONE);\r
+\r
+ t.executeAll();\r
+\r
+ assertEquals(Bit.ZERO, q.getValue());\r
+ assertEquals(Bit.ONE, nq.getValue());\r
+ }\r
+\r
+ @Test\r
+ void numericValueTest()\r
+ {\r
+ t.reset();\r
+\r
+ Wire a = new Wire(t, 4, 1);\r
+ a.createReadWriteEnd().feedSignals(Bit.ONE, Bit.ONE, Bit.ONE, Bit.ONE);\r
\r
- wI2.feedSignals(Bit.ZERO, Bit.Z);\r
- Simulation.TIMELINE.executeAll();\r
- assertBitArrayEquals(w.getValues(), Bit.X, Bit.Z);\r
+ t.executeAll();\r
\r
- wI2.feedSignals(Bit.Z, Bit.Z);\r
- Simulation.TIMELINE.executeAll();\r
- assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
+ assertEquals(15, a.getUnsignedValue());\r
+ assertEquals(-1, a.getSignedValue());\r
+ }\r
+\r
+ boolean flag = false;\r
+\r
+ @Test\r
+ void simpleTimelineTest()\r
+ {\r
+ Timeline t = new Timeline(3);\r
+ flag = false;\r
+ t.addEvent((e) ->\r
+ {\r
+ if (!flag)\r
+ fail();\r
+ flag = false;\r
+ }, 15);\r
+ t.addEvent((e) ->\r
+ {\r
+ if (flag)\r
+ fail();\r
+ flag = true;\r
+ }, 10);\r
+ t.addEvent((e) ->\r
+ {\r
+ if (flag)\r
+ fail();\r
+ flag = true;\r
+ }, 20);\r
+ t.addEvent((e) ->\r
+ {\r
+ fail("Only supposed to execute until timestamp 20, not 25");\r
+ }, 25);\r
+\r
+ t.executeUntil(t.laterThan(20), 100);\r
+\r
+ if (!flag)\r
+ fail();\r
+ }\r
\r
- wI2.feedSignals(Bit.ONE, Bit.Z);\r
- w.addObserver((i) -> fail("WireArray notified observer, although value did not change."));\r
- Simulation.TIMELINE.executeAll();\r
- assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
- }\r
+ @Test\r
+ void multipleInputs()\r
+ {\r
+ t.reset();\r
+ Wire w = new Wire(t, 2, 1);\r
+ ReadWriteEnd wI1 = w.createReadWriteEnd(), wI2 = w.createReadWriteEnd();\r
+ wI1.feedSignals(Bit.ONE, Bit.Z);\r
+ wI2.feedSignals(Bit.Z, Bit.X);\r
+ t.executeAll();\r
+ assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.X);\r
+\r
+ wI2.feedSignals(Bit.ZERO, Bit.Z);\r
+ t.executeAll();\r
+ assertBitArrayEquals(w.getValues(), Bit.X, Bit.Z);\r
+\r
+ wI2.feedSignals(Bit.Z, Bit.Z);\r
+ t.executeAll();\r
+ assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
+\r
+ wI2.feedSignals(Bit.ONE, Bit.Z);\r
+ ReadEnd rE = w.createReadOnlyEnd();\r
+ rE.addObserver((i, oldValues) -> fail("WireEnd notified observer, although value did not change."));\r
+ t.executeAll();\r
+ rE.close();\r
+ wI1.feedSignals(Bit.X, Bit.X);\r
+ t.executeAll();\r
+ wI1.addObserver((i, oldValues) -> fail("WireEnd notified observer, although it was closed."));\r
+ wI1.close();\r
+ assertBitArrayEquals(w.getValues(), Bit.ONE, Bit.Z);\r
+ }\r
\r
@Test\r
void wireConnections()\r
{\r
// Nur ein Experiment, was über mehrere 'passive' Bausteine hinweg passieren würde\r
- \r
- Simulation.TIMELINE.reset();\r
-\r
- WireArray a = new WireArray(1, 2);\r
- WireArray b = new WireArray(1, 2);\r
- WireArray c = new WireArray(1, 2);\r
- WireArrayInput aI = a.createInput();\r
- WireArrayInput bI = b.createInput();\r
- WireArrayInput cI = c.createInput();\r
-\r
- TestBitDisplay test = new TestBitDisplay(c);\r
- TestBitDisplay test2 = new TestBitDisplay(a);\r
+\r
+ t.reset();\r
+\r
+ Wire a = new Wire(t, 1, 2);\r
+ Wire b = new Wire(t, 1, 2);\r
+ Wire c = new Wire(t, 1, 2);\r
+ ReadWriteEnd aI = a.createReadWriteEnd();\r
+ ReadWriteEnd bI = b.createReadWriteEnd();\r
+ ReadWriteEnd cI = c.createReadWriteEnd();\r
+\r
+ TestBitDisplay test = new TestBitDisplay(t, c.createReadOnlyEnd());\r
+ TestBitDisplay test2 = new TestBitDisplay(t, a.createReadOnlyEnd());\r
LongConsumer print = time -> System.out.format("Time %2d\n a: %s\n b: %s\n c: %s\n", time, a, b, c);\r
\r
cI.feedSignals(Bit.ONE);\r
cI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
\r
- Connector c1 = new Connector(b, c);\r
+ new Connector(t, b.createReadWriteEnd(), c.createReadWriteEnd()).connect();\r
test.assertAfterSimulationIs(print, Bit.Z);\r
System.err.println("ONE");\r
bI.feedSignals(Bit.ONE);\r
System.err.println("Z");\r
bI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
- \r
- Connector c2 = new Connector(a, b);\r
+\r
+ new Connector(t, a.createReadWriteEnd(), b.createReadWriteEnd()).connect();\r
System.err.println("Z 2");\r
aI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
aI.feedSignals(Bit.Z);\r
test.assertAfterSimulationIs(print, Bit.Z);\r
test2.assertAfterSimulationIs(Bit.Z);\r
- \r
+\r
System.err.println("No Conflict yet");\r
bI.feedSignals(Bit.ONE);\r
test.assertAfterSimulationIs(print, Bit.ONE);\r
test2.assertAfterSimulationIs(Bit.ONE);\r
}\r
\r
- private static void assertBitArrayEquals(Bit[] actual, Bit... expected)\r
- {\r
- assertArrayEquals(expected, actual);\r
- }\r
+ private static void assertBitArrayEquals(BitVector actual, Bit... expected)\r
+ {\r
+ assertArrayEquals(expected, actual.getBits());\r
+ }\r
}\r