Generalized WireObserver to LogicObserver

[Mograsim.git] / net.mograsim.logic.core / src / net / mograsim / logic / core / components / gates / NotGate.java

diff --git a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java
index b1cfefe..e1c0e60 100644 (file)
--- a/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java
+++ b/net.mograsim.logic.core/src/net/mograsim/logic/core/components/gates/NotGate.java
@@ -1,50 +1,50 @@
-package net.mograsim.logic.core.components.gates;
-
-import java.util.List;
-
-import net.mograsim.logic.core.components.BasicComponent;
-import net.mograsim.logic.core.timeline.Timeline;
-import net.mograsim.logic.core.wires.Wire.ReadEnd;
-import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;
-
-public class NotGate extends BasicComponent
-{
-       private ReadEnd in;
-       private ReadWriteEnd out;
-
-       public NotGate(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out)
-       {
-               super(timeline, processTime);
-               this.in = in;
-               in.addObserver(this);
-               this.out = out;
-       }
-
-       @Override
-       protected void compute()
-       {
-               out.feedSignals(in.getValues().not());
-       }
-
-       public ReadEnd getIn()
-       {
-               return in;
-       }
-
-       public ReadEnd getOut()
-       {
-               return out;
-       }
-
-       @Override
-       public List<ReadEnd> getAllInputs()
-       {
-               return List.of(in);
-       }
-
-       @Override
-       public List<ReadWriteEnd> getAllOutputs()
-       {
-               return List.of(out);
-       }
-}
+package net.mograsim.logic.core.components.gates;\r
+\r
+import java.util.List;\r
+\r
+import net.mograsim.logic.core.components.BasicComponent;\r
+import net.mograsim.logic.core.timeline.Timeline;\r
+import net.mograsim.logic.core.wires.Wire.ReadEnd;\r
+import net.mograsim.logic.core.wires.Wire.ReadWriteEnd;\r
+\r
+public class NotGate extends BasicComponent\r
+{\r
+       private ReadEnd in;\r
+       private ReadWriteEnd out;\r
+\r
+       public NotGate(Timeline timeline, int processTime, ReadEnd in, ReadWriteEnd out)\r
+       {\r
+               super(timeline, processTime);\r
+               this.in = in;\r
+               in.registerObserver(this);\r
+               this.out = out;\r
+       }\r
+\r
+       @Override\r
+       protected void compute()\r
+       {\r
+               out.feedSignals(in.getValues().not());\r
+       }\r
+\r
+       public ReadEnd getIn()\r
+       {\r
+               return in;\r
+       }\r
+\r
+       public ReadEnd getOut()\r
+       {\r
+               return out;\r
+       }\r
+\r
+       @Override\r
+       public List<ReadEnd> getAllInputs()\r
+       {\r
+               return List.of(in);\r
+       }\r
+\r
+       @Override\r
+       public List<ReadWriteEnd> getAllOutputs()\r
+       {\r
+               return List.of(out);\r
+       }\r
+}\r