Serializing now serializes everything; among many other things:
[Mograsim.git] / net.mograsim.logic.model.editor / components / GUI_rsLatch.json
index a91b815..4199e45 100644 (file)
@@ -40,110 +40,115 @@ mograsim version: 0.1.3
     "innerScale": 0.4,
     "subComps": [
       {
+        "id": "GUINandGate",
+        "name": "GUINandGate#1",
         "pos": {
           "x": 40.0,
           "y": 12.5
         },
-        "id": "GUINandGate",
-        "name": "GUINandGate#1",
         "params": 1
       },
       {
+        "id": "GUINandGate",
+        "name": "GUINandGate#0",
         "pos": {
           "x": 10.0,
           "y": 7.5
         },
-        "id": "GUINandGate",
-        "name": "GUINandGate#0",
         "params": 1
       },
       {
+        "id": "WireCrossPoint",
+        "name": "WireCrossPoint#1",
         "pos": {
           "x": 64.0,
           "y": 36.5
         },
-        "id": "WireCrossPoint",
-        "name": "WireCrossPoint#1",
         "params": 1
       },
       {
+        "id": "WireCrossPoint",
+        "name": "WireCrossPoint#0",
         "pos": {
           "x": 34.0,
           "y": 16.5
         },
-        "id": "WireCrossPoint",
-        "name": "WireCrossPoint#0",
         "params": 1
       }
     ],
     "innerWires": [
       {
         "pin1": {
-          "compName": "_submodelinterface",
-          "pinName": "_S"
+          "compName": "WireCrossPoint#0",
+          "pinName": ""
         },
         "pin2": {
-          "compName": "GUINandGate#0",
-          "pinName": "A"
-        },
-        "path": []
-      },
-      {
-        "pin1": {
           "compName": "_submodelinterface",
-          "pinName": "_R"
-        },
-        "pin2": {
-          "compName": "GUINandGate#1",
-          "pinName": "B"
+          "pinName": "Q"
         },
+        "name": "q",
         "path": [
           {
             "x": 35.0,
-            "y": 37.5
+            "y": 17.5
           },
           {
             "x": 35.0,
-            "y": 27.5
+            "y": 7.5
+          },
+          {
+            "x": 65.0,
+            "y": 7.5
+          },
+          {
+            "x": 65.0,
+            "y": 12.5
           }
         ]
       },
       {
         "pin1": {
-          "compName": "GUINandGate#0",
-          "pinName": "Y"
+          "compName": "WireCrossPoint#1",
+          "pinName": ""
         },
         "pin2": {
-          "compName": "WireCrossPoint#0",
-          "pinName": ""
+          "compName": "_submodelinterface",
+          "pinName": "_Q"
         },
+        "name": "_q",
         "path": []
       },
       {
         "pin1": {
-          "compName": "GUINandGate#1",
-          "pinName": "Y"
+          "compName": "_submodelinterface",
+          "pinName": "_R"
         },
         "pin2": {
-          "compName": "WireCrossPoint#1",
-          "pinName": ""
+          "compName": "GUINandGate#1",
+          "pinName": "B"
         },
+        "name": "unnamedWire#1",
         "path": [
           {
-            "x": 65.0,
-            "y": 22.5
+            "x": 35.0,
+            "y": 37.5
+          },
+          {
+            "x": 35.0,
+            "y": 27.5
           }
         ]
       },
       {
         "pin1": {
-          "compName": "WireCrossPoint#0",
-          "pinName": ""
+          "compName": "_submodelinterface",
+          "pinName": "_S"
         },
         "pin2": {
-          "compName": "GUINandGate#1",
+          "compName": "GUINandGate#0",
           "pinName": "A"
         },
+        "name": "unnamedWire#0",
         "path": []
       },
       {
@@ -155,6 +160,7 @@ mograsim version: 0.1.3
           "compName": "GUINandGate#0",
           "pinName": "B"
         },
+        "name": "unnamedWire#5",
         "path": [
           {
             "x": 65.0,
@@ -176,47 +182,67 @@ mograsim version: 0.1.3
           "pinName": ""
         },
         "pin2": {
-          "compName": "_submodelinterface",
-          "pinName": "Q"
+          "compName": "GUINandGate#1",
+          "pinName": "A"
+        },
+        "name": "unnamedWire#4",
+        "path": []
+      },
+      {
+        "pin1": {
+          "compName": "GUINandGate#1",
+          "pinName": "Y"
+        },
+        "pin2": {
+          "compName": "WireCrossPoint#1",
+          "pinName": ""
         },
+        "name": "unnamedWire#3",
         "path": [
-          {
-            "x": 35.0,
-            "y": 17.5
-          },
-          {
-            "x": 35.0,
-            "y": 7.5
-          },
           {
             "x": 65.0,
-            "y": 7.5
-          },
-          {
-            "x": 65.0,
-            "y": 12.5
+            "y": 22.5
           }
         ]
       },
       {
         "pin1": {
-          "compName": "WireCrossPoint#1",
-          "pinName": ""
+          "compName": "GUINandGate#0",
+          "pinName": "Y"
         },
         "pin2": {
-          "compName": "_submodelinterface",
-          "pinName": "_Q"
+          "compName": "WireCrossPoint#0",
+          "pinName": ""
         },
+        "name": "unnamedWire#2",
         "path": []
       }
     ]
   },
-  "symbolRendererSnippetID": "SimpleRectangularLikeSymbolRenderer",
+  "symbolRendererSnippetID": "class:net.mograsim.logic.model.snippets.symbolrenderers.SimpleRectangularLikeSymbolRenderer",
   "symbolRendererParams": {
     "centerText": "_rsLatch",
-    "horizontalComponentCenter": 17.5,
     "centerTextHeight": 5.0,
+    "horizontalComponentCenter": 17.5,
     "pinLabelHeight": 3.5,
     "pinLabelMargin": 0.5
+  },
+  "outlineRendererSnippetID": "class:net.mograsim.logic.model.snippets.outlinerenderers.DefaultOutlineRenderer",
+  "highLevelStateHandlerSnippetID": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.StandardHighLevelStateHandler",
+  "highLevelStateHandlerParams": {
+    "subcomponentHighLevelStates": {},
+    "atomicHighLevelStates": {
+      "q": {
+        "id": "class:net.mograsim.logic.model.snippets.highlevelstatehandlers.standard.atomic.WireForcingAtomicHighLevelStateHandler",
+        "params": {
+          "wiresToForce": [
+            "q"
+          ],
+          "wiresToForceInverted": [
+            "_q"
+          ]
+        }
+      }
+    }
   }
 }
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