Changed high level addressing to have the correct bit and reg. order

[Mograsim.git] / net.mograsim.logic.ui.am2900 / src / net / mograsim / logic / ui / model / components / mi / nandbased / GUI_rsLatch.java

diff --git a/net.mograsim.logic.ui.am2900/src/net/mograsim/logic/ui/model/components/mi/nandbased/GUI_rsLatch.java b/net.mograsim.logic.ui.am2900/src/net/mograsim/logic/ui/model/components/mi/nandbased/GUI_rsLatch.java
index 3d2d8ce..a7f8025 100644 (file)
--- a/net.mograsim.logic.ui.am2900/src/net/mograsim/logic/ui/model/components/mi/nandbased/GUI_rsLatch.java
+++ b/net.mograsim.logic.ui.am2900/src/net/mograsim/logic/ui/model/components/mi/nandbased/GUI_rsLatch.java
@@ -86,7 +86,7 @@ public class GUI_rsLatch extends SimpleRectangularSubmodelComponent
                {
                case "q":
                        if (wireQ.hasLogicModelBinding())
-                               return wireQ.getWireValues().getBit(0);
+                               return wireQ.getWireValues().getBit(0).join(wire_Q.getWireValues().getBit(0).not());
                        return null;
                default:
                        return super.getHighLevelState(stateID);