Changed high level addressing to have the correct bit and reg. order
[Mograsim.git] / net.mograsim.logic.ui.am2900 / src / net / mograsim / logic / ui / model / components / mi / nandbased / GUIdlatch4.java
index 8da90e1..61a239a 100644 (file)
@@ -91,10 +91,10 @@ public class GUIdlatch4 extends SimpleRectangularSubmodelComponent
                        break;
                case "q":
                        BitVector newStateCasted = (BitVector) newState;
-                       setHighLevelState("q1", newStateCasted.getBit(0));
-                       setHighLevelState("q2", newStateCasted.getBit(1));
-                       setHighLevelState("q3", newStateCasted.getBit(2));
-                       setHighLevelState("q4", newStateCasted.getBit(3));
+                       setHighLevelState("q1", newStateCasted.getBit(3));
+                       setHighLevelState("q2", newStateCasted.getBit(2));
+                       setHighLevelState("q3", newStateCasted.getBit(1));
+                       setHighLevelState("q4", newStateCasted.getBit(0));
                        break;
                default:
                        super.setHighLevelState(stateID, newState);
@@ -120,7 +120,7 @@ public class GUIdlatch4 extends SimpleRectangularSubmodelComponent
                        Bit q2 = (Bit) getHighLevelState("q2");
                        Bit q3 = (Bit) getHighLevelState("q3");
                        Bit q4 = (Bit) getHighLevelState("q4");
-                       return BitVector.of(q1, q2, q3, q4);
+                       return BitVector.of(q4, q3, q2, q1);
                default:
                        return super.getHighLevelState(stateID);
                }